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Highly contributed researchers

In recent 10 years: Kenichi Okada (22)

Tadahiro Kuroda (19) / Akira Matsuzawa (18) / Takayasu Sakurai (17) / Makoto Takamiya (16) / Ken Takeuchi (16)

Since 2007: Tadahiro Kuroda (29)

Takayasu Sakurai (24) / Kenichi Okada (23) / Makoto Takamiya (19) / Akira Matsuzawa (18) / Ken Takeuchi (18)

Statistics

A 10-mW 16-b 15-MS/s Two-Step SAR ADC With 95-dB DR Using Dual-Deadzone Ring Amplifier

Authors: Ahmed ElShater, Praveen Kumar Venkatachala, Calvin Yoji Lee, Jason Muhlestein, Spencer Leuenberger, Kazuki Sobue, Koichi Hamashita, Un-Ku Moon

A Self-Calibrated 16-GHz Subsampling-PLL-Based Fast-Chirp FMCW Modulator With 1.5-GHz Bandwidth

Authors: Qixian Shi, Keigo Bunsen, Nereo Markulic, Jan Craninckx

An 80-Gb/s 300-GHz-Band Single-Chip CMOS Transceiver

Authors: Sangyeop Lee, Shinsuke Hara, Takeshi Yoshida, Shuhei Amakawa, Ruibing Dong, Akifumi Kasamatsu, Junji Sato, Minoru Fujishima

A 265- $\mu$ W Fractional- ${N}$ Digital PLL With Seamless Automatic Switching Sub-Sampling/Sampling Feedback Path and Duty-Cycled Frequency-Locked Loop in 65-nm CMOS

Authors: Hanli Liu, Atsushi Shirane, Kenichi Okada, Zheng Sun, Hongye Huang, Wei Deng, Teerachot Siriburanon, Jian Pang, Yun Wang, Rui Wu, Teruki Someya

A 42.2-Gb/s 4.3-pJ/b 60-GHz Digital Transmitter With 12-b/Symbol Polarization MIMO

Authors: Chintan Thakkar, Anandaroop Chakrabarti, Shuhei Yamada, Debabani Choudhury, James E. Jaussi, Bryan Casper

A Modular, Direct Time-of-Flight Depth Sensor in 45/65-nm 3-D-Stacked CMOS Technology

Authors: Augusto Ronchini Ximenes, Preethi Padmanabhan, Myung-Jae Lee, Yuichiro Yamashita, Dun-Nian Yaung, Edoardo Charbon

A 47.14-W 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications

Authors: Masanori Natsui, Daisuke Suzuki, Akira Tamakoshi, Toshinari Watanabe, Hiroaki Honjo, Hiroki Koike, Takashi Nasuno, Yitao Ma, Takaho Tanigawa, Yasuo Noguchi, Mitsuo Yasuhira, Hideo Sato, Shoji Ikeda, Hideo Ohno, Tetsuo Endoh, Takahiro Hanyu

ULPAC: A Miniaturized Ultralow-Power Atomic Clock

Authors: Haosheng Zhang, Hans Herdian, Aravind Tharayil Narayanan, Atsushi Shirane, Mitsuru Suzuki, Kazuhiro Harasaka, Kazuhiko Adachi, Shigeyoshi Goka, Shinya Yanagimachi, Kenichi Okada

A Single-Chip Optical Phased Array in a Wafer-Scale Silicon Photonics/CMOS 3D-Integration Platform

Authors: Taehwan Kim, Pavan Bhargava, Christopher V. Poulton, Jelena Notaros, Ami Yaacobi, Erman Timurdogan, Christopher Baiocco, Nicholas Fahrenkopf, Seth Kruger, Tat Ngai, Yukta Timalsina, Michael R. Watts, Vladimir Stojanovic

An 8 Bit 12.4 TOPS/W Phase-Domain MAC Circuit for Energy-Constrained Deep Learning Accelerators

Authors: Yosuke Toyama, Kentaro Yoshioka, Koichiro Ban, Shigeru Maya, Akihide Sai, Kohei Onizuka

A 28-nm 320-Kb TCAM Macro Using Split-Controlled Single-Load 14T Cell and Triple-Margin Voltage Sense Amplifier

Authors: Cheng-Xin Xue, Wei-Cheng Zhao, Tzu-Hsien Yang, Yi-Ju Chen, Hiroyuki Yamauchi, Meng-Fan Chang

A 0.25-27-Gb/s PAM4/NRZ Transceiver With Adaptive Power CDR and Jitter Analysis

Authors: Yoshihide Komatsu, Akinori Shinmyo, Shuji Kato, Masami Funabashi, Kazuya Hatooka, Mayuko Fujita, Kenji Tanaka, Aoi Yamasaki, Kouichi Fukuda

Single-Chip 3072-Element-Channel Transceiver/128-Subarray-Channel 2-D Array IC With Analog RX and All-Digital TX Beamformer for Echocardiography

Authors: Yutaka Igarashi, Shinya Kajiyama, Yusaku Katsube, Takuma Nishimoto, Tatsuo Nakagawa, Yasuyuki Okuma, Yohei Nakamura, Takahide Terada, Taizo Yamawaki, Toru Yazaki, Yoshihiro Hayashi, Kazuhiro Amino, Takuya Kaneko, Hiroki Tanaka

5-31-Hz 188- $\mu$ W Light-Sensing Oscillator With Two Active Inductors Fully Integrated on Plastic

Authors: Tilo Meister, Koichi Ishida, Stefan Knobelspies, Giuseppe Cantarella, Niko Mnzenrieder, Gerhard Trster, Corrado Carta, Frank Ellinger

3-D NAND Flash Value-Aware SSD: Error-Tolerant SSD Without ECCs for Image Recognition

Authors: Yoshiaki Deguchi, Toshiki Nakamura, Atsuna Hayakawa, Ken Takeuchi

A 28-GHz CMOS Phased-Array Transceiver Based on LO Phase-Shifting Architecture With Gain Invariant Phase Tuning for 5G New Radio

Authors: Jian Pang, Rui Wu, Yun Wang, Masato Dome, Hisashi Kato, Hongye Huang, Aravind Tharayil Narayanan, Hanli Liu, Bangan Liu, Takeshi Nakamura, Takuya Fujimura, Masaru Kawabuchi, Ryo Kubozoe, Tsuyoshi Miura, Daiki Matsumoto, Zheng Li, Naoki Oshima, Keiichi Motoi, Shinichi Hori, Kazuaki Kunihiro, Tomoya Kaneko, Atsushi Shirane, Kenichi Okada

A 60-GHz 3.0-Gb/s Spectrum Efficient BPOOK Transceiver for Low-Power Short-Range Wireless in 65-nm CMOS

Authors: Yun Wang, Bangan Liu, Rui Wu, Hanli Liu, Aravind Tharayil Narayanan, Jian Pang, Ning Li, Toru Yoshioka, Yuki Terashima, Haosheng Zhang, Dexian Tang, Makihiko Katsuragi, Daeyoung Lee, Sung Tae Choi, Kenichi Okada, Akira Matsuzawa

A 50.1-Gb/s 60-GHz CMOS Transceiver for IEEE 802.11ay With Calibration of LO Feedthrough and I/Q Imbalance

Authors: Jian Pang, Shotaro Maki, Seitarou Kawai, Noriaki Nagashima, Yuuki Seo, Masato Dome, Hisashi Kato, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Yuki Terashima, Hanli Liu, Teerachot Siriburanon, Aravind Tharayil Narayanan, Nurul Fajri, Tohru Kaneko, Toru Yoshioka, Bangan Liu, Yun Wang, Rui Wu, Ning Li, Korkut Kaan Tokgoz, Masaya Miyahara, Atsushi Shirane, Kenichi Okada

A Time-Resolved NIR Lock-In Pixel CMOS Image Sensor With Background Cancelling Capability for Remote Heart Rate Detection

Authors: Chen Cao, Yuya Shirakawa, Leyi Tan, Min-Woong Seo, Keiichiro Kagawa, Keita Yasutomi, Sung-Wook Jun, Tomohiko Kosugi, Satoshi Aoyama, Nobukazu Teranishi, Norimichi Tsumura, Shoji Kawahito

A 12.8-Gb/s Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth, Large-Capacity Storage Systems

Authors: Yuta Tsubouchi, Daisuke Miyashita, Takashi Toi, Yuji Satoh, Fumihiko Tachibana, Junji Wadatsumi, Makoto Morimoto, Ryuichi Fujimoto, Jun Deguchi

A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR- and IIR-Tap Adaptation in 65-nm CMOS

Authors: Ashkan Roshan-Zamir, Takayuki Iwai, Yang-Hang Fan, Ankur Kumar, Hae-Woong Yang, Lee Sledjeski, John Hamilton, Soumya Chandramouli, Arlo Aude, Samuel Palermo

A 130-nm Ferroelectric Nonvolatile System-on-Chip With Direct Peripheral Restore Architecture for Transient Computing System

Authors: Yongpan Liu, Fang Su, Yixiong Yang, Zhibo Wang, Yiqun Wang, Zewei Li, Xueqing Li, Ryuji Yoshimura, Takashi Naiki, Takashi Tsuwa, Takahiko Saito, Zhongjun Wang, Koji Taniuchi, Huazhong Yang

An 11-nW CMOS Temperature-to-Digital Converter Utilizing Sub-Threshold Current at Sub-Thermal Drain Voltage

Authors: Teruki Someya, A. K. M. Mahfuzul Islam, Takayasu Sakurai, Makoto Takamiya

A 7T-SRAM With Data-Write Technique by Capacitive Coupling

Authors: Daisaburo Takashima, Masato Endo, Kazuhiro Shimazaki, Manabu Sai, Masaaki Tanino

QUEST: Multi-Purpose Log-Quantized DNN Inference Engine Stacked on 96-MB 3-D SRAM Using Inductive Coupling Technology in 40-nm CMOS

Authors: Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Shinya Takamaeda-Yamazaki, Mototsugu Hamada, Tadahiro Kuroda, Masato Motomura

A DPLL-Centric Bluetooth Low-Energy Transceiver With a 2.3-mW Interference-Tolerant Hybrid-Loop Receiver in 65-nm CMOS

Authors: Hanli Liu, Zheng Sun, Dexian Tang, Hongye Huang, Tohru Kaneko, Zhijie Chen, Wei Deng, Rui Wu, Kenichi Okada

An 802.11ax 4 4 High-Efficiency WLAN AP Transceiver SoC Supporting 1024-QAM With Frequency-Dependent IQ Calibration and Integrated Interference Analyzer

Authors: Shusuke Kawai, Rui Ito, Kengo Nakata, Yutaka Shimizu, Motoki Nagata, Tomohiko Takeuchi, Hiroyuki Kobayashi, Katsuyuki Ikeuchi, Takayuki Kato, Yosuke Hagiwara, Yuki Fujimura, Kentaro Yoshioka, Shigehito Saigusa, Hiroshi Yoshida, Makoto Arai, Toshiyuki Yamagishi, Hirotsugu Kajihara, Kazuhisa Horiuchi, Hideki Yamada, Tomoya Suzuki, Yuki Ando, Kensuke Nakanishi, Koichiro Ban, Masahiro Sekiya, Yoshimasa Egashira, Tsuguhide Aoki, Kohei Onizuka, Toshiya Mitomo

A 60-GHz 144-Element Phased-Array Transceiver for Backhaul Application

Authors: Tirdad Sowlati, Saikat Sarkar, Bevin George Perumana, Wei Liat Chan, Anna Papio Toda, Bagher Afshar, Michael Boers, Donghyup Shin, Timothy Mercer, Wei-Hong Chen, Alfred Grau Besoli, Seunghwan Yoon, Sissy Kyriazidou, Phil Yang, Vipin Aggarwal, Nooshin Vakilian, Dmitriy Rozenblit, Masoud Kahrizi, Joy Zhang, Alan Wang, Padmanava Sen, David Murphy, Ali Sajjadi, Alireza Tarighat Mehrabani, Evangelos Kornaros, Khim Low, Koji Kimura, Vincent Roussel, Hongyu Xie, Venkat Kodavati

A Sub-mW Fractional-N ADPLL With FOM of -246 dB for IoT Applications

Authors: Hanli Liu, Dexian Tang, Zheng Sun, Wei Deng, Huy Cu Ngo, Kenichi Okada

A 60-GHz Transceiver and Baseband With Polarization MIMO in 28-nm CMOS

Authors: Kaushik Dasgupta, Saeid Daneshgar, Chintan Thakkar, Shinwon Kang, Anandaroop Chakrabarti, Shuhei Yamada, Nathan Narevsky, Debabani Choudhury, James E. Jaussi, Bryan Casper

A 286 F2/Cell Distributed Bulk-Current Sensor and Secure Flush Code Eraser Against Laser Fault Injection Attack on Cryptographic Processor

Authors: Kohei Matsuda, Tatsuya Fujii, Natsu Shoji, Takeshi Sugawara, Kazuo Sakiyama, Yu-ichi Hayashi, Makoto Nagata, Noriyuki Miura

A 6.9-m Pixel-Pitch Back-Illuminated Global Shutter CMOS Image Sensor With Pixel-Parallel 14-Bit Subthreshold ADC

Authors: Masaki Sakakibara, Koji Ogawa, Shin Sakai, Yasuhisa Tochigi, Katsumi Honda, Hidekazu Kikuchi, Takuya Wada, Yasunobu Kamikubo, Tsukasa Miura, Masahiko Nakamizo, Naoki Jyo, Ryo Hayashibara, Shinya Miyata, Satoshi Yamamoto, Yoshiyuki Ota, Hirotsugu Takahashi, Tadayuki Taura, Yusuke Oike, Keiji Tatani, Takayuki Ezaki, Teruo Hirayama

A 20-ch TDC/ADC Hybrid Architecture LiDAR SoC for 240 96 Pixel 200-m Range Imaging With Smart Accumulation Technique and Residue Quantizing SAR ADC

Authors: Kentaro Yoshioka, Hiroshi Kubota, Tomonori Fukushima, Satoshi Kondo, Tuan Thanh Ta, Hidenori Okuni, Kaori Watanabe, Masatoshi Hirono, Yoshinari Ojima, Katsuyuki Kimura, Sohichiroh Hosoda, Yutaka Ota, Tomohiro Koizumi, Naoyuki Kawabe, Yasuhiro Ishii, Yoichiro Iwagami, Seitaro Yagi, Isao Fujisawa, Nobuo Kano, Tomohiko Sugimoto, Daisuke Kurose, Naoya Waki, Yumi Higashi, Tetsuya Nakamura, Yoshikazu Nagashima, Hirotomo Ishii, Akihide Sai, Nobu Matsumoto

Chip-Package-Board Interactive PUF Utilizing Coupled Chaos Oscillators With Inductor

Authors: Noriyuki Miura, Masanori Takahashi, Kazuki Nagatomo, Makoto Nagata

A 12.8-ns-Latency DDFS MMIC With Frequency, Phase, and Amplitude Modulations in 65-nm CMOS

Authors: Abdel Martinez Alonso, Masaya Miyahara, Akira Matsuzawa

Loop Gain Adaptation for Optimum Jitter Tolerance in Digital CDRs

Authors: Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Yuuki Ogata, Hisakatsu Yamaguchi

A Time-Resolved Four-Tap Lock-In Pixel CMOS Image Sensor for Real-Time Fluorescence Lifetime Imaging Microscopy

Authors: Min-Woong Seo, Yuya Shirakawa, Yoshimasa Kawata, Keiichiro Kagawa, Keita Yasutomi, Shoji Kawahito

A 50-Gb/s High-Sensitivity (-9.2 dBm) Low-Power (7.9 pJ/bit) Optical Receiver Based on 0.18-m SiGe BiCMOS Technology

Authors: Takashi Takemoto, Yasunobu Matsuoka, Hiroki Yamashita, Yong Lee, Hideo Arimoto, Masaru Kokubo, Tatemi Ido

A Stacked CMOS Image Sensor With Array-Parallel ADC Architecture

Authors: Tomohiro Takahashi, Yuichi Kaji, Yasunori Tsukuda, Shinichiro Futami, Katsuhiko Hanzawa, Takahito Yamauchi, Ping Wah Wong, Frederick T. Brady, Phil Holden, Thomas Ayers, Kyohei Mizuta, Susumu Ohki, Keiji Tatani, Hayato Wakabayashi, Yoshikazu Nitta

An Adaptive-Clocking-Control Circuit With 7.5% Frequency Gain for SPARC Processors

Authors: Tetsutaro Hashimoto, Yukihito Kawabe, Michiharu Hara, Yasushi Kakimura, Kunihiko Tajiri, Shinichiro Shirota, Ryuichi Nishiyama, Hitoshi Sakurai, Hiroshi Okano, Yasumoto Tomita, Sugio Satoh, Hideo Yamashita

A 4 + 2T SRAM for Searching and In-Memory Computing With 0.3-V VDDmin

Authors: Qing Dong, Supreet Jeloka, Mehdi Saligane, Yejoong Kim, Masaru Kawaminami, Akihiko Harada, Satoru Miyoshi, Makoto Yasuda, David T. Blaauw, Dennis Sylvester

A Miniaturized Single-Transducer Implantable Pressure Sensor With Time-Multiplexed Ultrasonic Data and Power Links

Authors: Marcus J. Weber, Yoshiaki Yoshihara, Ahmed Sawaby, Jayant Charthad, Ting Chia Chang, Amin Arbabian

BRein Memory: A Single-Chip Binary/Ternary Reconfigurable in-Memory Deep Neural Network Accelerator Achieving 1.4 TOPS at 0.6 W

Authors: Kota Ando, Kodai Ueyoshi, Kentaro Orimo, Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura

320 240 Back-Illuminated 10-m CAPD Pixels for High-Speed Modulation Time-of-Flight CMOS Image Sensor

Authors: Yuichi Kato, Takuya Sano, Yusuke Moriyama, Shunji Maeda, Takeshi Yamazaki, Atsushi Nose, Kimiyasu Shiina, Yohtaro Yasu, Ward van der Tempel, Alper Ercan, Yoshiki Ebiko, Daniel Van Nieuwenhove, Shunichi Sukegawa

A 16-bit 16-MS/s SAR ADC With On-Chip Calibration in 55-nm CMOS

Authors: Junhua Shen, Akira Shikata, Lalinda Fernando, Ned Guthrie, Baozhen Chen, Mark Maddox, Nikhil Mascarenhas, Ron Kapusta, Michael C. W. Coln

80-kb Logic Embedded High-K Charge Trap Transistor-Based Multi-Time-Programmable Memory With No Added Process Complexity

Authors: Balaji Jayaraman, Derek Leu, Janakiraman Viraraghavan, Alberto Cestero, Ming Yin, John Golz, Rajesh Reddy Tummuru, Ramesh Raghavan, Dan Moy, Thejas Kempanna, Faraz Khan, Toshiaki Kirihata, Subramanian S. Iyer

A Digital Filtering ADC With Programmable Blocker Cancellation for Wireless Receivers

Authors: Qiwei Wang, Hajime Shibata, Antonio Liscidini, Anthony Chan Carusone

On-Chip Jitter Measurement Using Jitter Injection in a 28 Gb/s PI-Based CDR

Authors: Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Hisakatsu Yamaguchi

A 1.8e $^{-}_{\mathrm {rms}} $ Temporal Noise Over 110-dB-Dynamic Range 3.4 $\mu \text{m}$ Pixel Pitch Global-Shutter CMOS Image Sensor With Dual-Gain Amplifiers SS-ADC, Light Guide Structure, and Multiple-Accumulation Shutter

Authors: Masahiro Kobayashi, Yusuke Onuki, Kazunari Kawabata, Hiroshi Sekine, Toshiki Tsuboi, Takashi Muto, Takeshi Akiyama, Yasushi Matsuno, Hidekazu Takahashi, Toru Koizumi, Katsuhito Sakurai, Hiroshi Yuzurihara, Shunsuke Inoue, Takeshi Ichikawa

A 2.1-Mpixel Organic Film-Stacked RGB-IR Image Sensor With Electrically Controllable IR Sensitivity

Authors: Shin'ichi Machida, Sanshiro Shishido, Takeyoshi Tokuhara, Masaaki Yanagida, Takayoshi Yamada, Masumi Izuchi, Yoshiaki Sato, Yasuo Miyake, Manabu Nakata, Masashi Murakami, Mitsuru Harada, Yasunori Inoue

Introduction to the January Special Issue on the 2017 IEEE International Solid-State Circuits Conference

Authors: Keith A. Bowman, Muhammad M. Khellah, Takashi Kono, Joseph Shor, Pui-In Mak

A 22.5-to-32-Gb/s 3.2-pJ/b Referenceless Baud-Rate Digital CDR With DFE and CTLE in 28-nm CMOS

Authors: Wahid Rahman, Danny Yoo, Joshua Liang, Ali Sheikholeslami, Hirotaka Tamura, Takayuki Shibasaki, Hisakatsu Yamaguchi

A 9-GS/s 1.125-GHz BW Oversampling Continuous-Time Pipeline ADC Achieving -164-dBFS/Hz NSD

Authors: Hajime Shibata, Victor Kozlov, Zexi Ji, Asha Ganesan, Haiyang Zhu, Donald Paterson, Jialin Zhao, Sharvil Patil, Shanthi Pavan

A Low-Power CMOS Crystal Oscillator Using a Stacked-Amplifier Architecture

Authors: Shunta Iguchi, Takayasu Sakurai, Makoto Takamiya

64-QAM 60-GHz CMOS Transceivers for IEEE 802.11ad/ay

Authors: Rui Wu, Ryo Minami, Yuuki Tsukui, Seitaro Kawai, Yuuki Seo, Shinji Sato, Kento Kimura, Satoshi Kondo, Tomohiro Ueno, Nurul Fajri, Shoutarou Maki, Noriaki Nagashima, Yasuaki Takeuchi, Tatsuya Yamaguchi, Ahmed Musa, Korkut Kaan Tokgoz, Teerachot Siriburanon, Bangan Liu, Yun Wang, Jian Pang, Ning Li, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

A 76- to 81-GHz Multi-Channel Radar Transceiver

Authors: Takeji Fujibayashi, Yohsuke Takeda, Weihu Wang, Yi-Shin Yeh, Willem Stapelbroek, Seiji Takeuchi, Brian A. Floyd

A Compact-Area Low-VDDmin 6T SRAM With Improvement in Cell Stability, Read Speed, and Write Margin Using a Dual-Split-Control-Assist Scheme

Authors: Meng-Fan Chang, Chien-Fu Chen, Ting-Hao Chang, Chi-Chang Shuai, Yen-Yao Wang, Yi-Ju Chen, Hiroyuki Yamauchi

A 58-nm 2-Gb MLC "B4-Flash" Memory with Flexible Multisector Architecture

Authors: Taku Ogura, Yasushi Kasa, Kazuhide Kurosaki, Mitsuhiro Tomoeda, Hisakazu Otoi, Satoshi Shimizu, Masafumi Katsumata, Natsuo Ajika, Kazuo Kobayashi

A 1-3 GHz Delta-Sigma-Based Closed-Loop Fully Digital Phase Modulator in 45-nm CMOS SOI

Authors: Hamed Gheidi, Toshifumi Nakatani, Vincent W. Leung, Peter M. Asbeck

A - 244-dB FOM High-Frequency Piezoelectric Resonator-Based Cascaded Fractional-N PLL With Sub-ppb-Order Channel-Adjusting Technique

Authors: Sho Ikeda, Hiroyuki Ito, Akifumi Kasamatsu, Yosuke Ishikawa, Takayoshi Obara, Naoki Noguchi, Koji Kamisuki, Yao Jiyang, Shinsuke Hara, Ruibing Dong, Shiro Dosho, Noboru Ishihara, Kazuya Masu

Embedded Memory and ARM Cortex-M0 Core Using 60-nm C-Axis Aligned Crystalline Indium-Gallium-Zinc Oxide FET Integrated With 65-nm Si CMOS

Authors: Tatsuya Onuki, Wataru Uesugi, Atsuo Isobe, Yoshinori Ando, Satoru Okamoto, Kiyoshi Kato, Tri Rung Yew, J. Y. Wu, Chi Chang Shuai, Shao Hui Wu, James Myers, Klaus Doppler, Masahiro Fujita, Shunpei Yamazaki

8.3 M-Pixel 480-fps Global-Shutter CMOS Image Sensor with Gain-Adaptive Column ADCs and Chip-on-Chip Stacked Integration

Authors: Yusuke Oike, Kentaro Akiyama, Luong D. Hung, Wataru Niitsuma, Akihiko Kato, Mamoru Sato, Yuri Kato, Wataru Nakamura, Hiroshi Shiroshita, Yorito Sakano, Yoshiaki Kitano, Takuya Nakamura, Takayuki Toyama, Hayato Iwamoto, Takayuki Ezaki

Introduction to the January Special Issue on the 2016 IEEE International Solid-State Circuits Conference

Authors: Dennis Sylvester, Dejan Markovic, Roman Genov, Atsushi Kawasumi, Subhasish Mitra

A 16 nm FinFET Heterogeneous Nona-Core SoC Supporting ISO26262 ASIL B Standard

Authors: Shinichi Shibahara, Chikafumi Takahashi, Kazuki Fukuoka, Yuko Kitaji, Takahiro Irita, Hirotaka Hara, Yasuhisa Shimazaki, Jun Matsushima

An 8K H.265/HEVC Video Decoder Chip With a New System Pipeline Design

Authors: Dajiang Zhou, Shihao Wang, Heming Sun, Jian-Bin Zhou, Jiayi Zhu, Yijin Zhao, Jinjia Zhou, Shuping Zhang, Shinji Kimura, Takeshi Yoshimura, Satoshi Goto

Electronic-Photonic Integrated Circuit for 3D Microimaging

Authors: Behnam Behroozpour, Phillip A. M. Sandborn, Niels Quack, Tae Joon Seok, Yasuhiro Matsui, Ming C. Wu, Bernhard E. Boser

A 0.5-9.5-GHz, 1.2-s Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling

Authors: Fazil Ahmad, Greg Unruh, Amrutha Iyer, Pin-En Su, Sherif Abdalla, Bo Shen, Mark Chambers, Ichiro Fujimori

A 72 dB-DR 465 MHz-BW Continuous-Time 1-2 MASH ADC in 28 nm CMOS

Authors: Yunzhi Dong, Jialin Zhao, Wenhua Yang, Trevor C. Caldwell, Hajime Shibata, Zhao Li, Richard Schreier, Qingdong Meng, Jos B. Silva, Donald Paterson, Jeffrey C. Gealow

A 5.5 mW ADPLL-Based Receiver With a Hybrid Loop Interference Rejection for BLE Application in 65 nm CMOS

Authors: Akihide Sai, Hidenori Okuni, Tuan Thanh Ta, Satoshi Kondo, Takashi Tokairin, Masanori Furuta, Tetsuro Itakura

A 12 Gb/s 0.9 mW/Gb/s Wide-Bandwidth Injection-Type CDR in 28 nm CMOS With Reference-Free Frequency Capture

Authors: Takashi Masuda, Ryota Shinoda, Jeremy Chatwin, Jacob Wysocki, Koki Uchino, Yoshifumi Miyajima, Yosuke Ueno, Kenichi Maruko, Zhiwei Zhou, Hideyuki Suzuki, Norio Shoji

A 300 GHz CMOS Transmitter With 32-QAM 17.5 Gb/s/ch Capability Over Six Channels

Authors: Kosuke Katayama, Kyoya Takano, Shuhei Amakawa, Shinsuke Hara, Akifumi Kasamatsu, Koichi Mizuno, Kazuaki Takahashi, Takeshi Yoshida, Minoru Fujishima

CMOS Biosensor IC Focusing on Dielectric Relaxations of Biological Water With 120 and 60 GHz Oscillator Arrays

Authors: Takeshi Mitsunaka, Daiki Sato, Nobuyuki Ashida, Akira Saito, Kunihiko Iizuka, Tetsuhito Suzuki, Yuichi Ogawa, Minoru Fujishima

Fully-Integrated High-Conversion-Ratio Dual-Output Voltage Boost Converter With MPPT for Low-Voltage Energy Harvesting

Authors: Toshihiro Ozaki, Tetsuya Hirose, Hiroki Asano, Nobutaka Kuroki, Masahiro Numa

A 9-bit 1.8 GS/s 44 mW Pipelined ADC Using Linearized Open-Loop Amplifiers

Authors: Lilan Yu, Masaya Miyahara, Akira Matsuzawa

A 3.6 GHz Low-Noise Fractional-N Digital PLL Using SAR-ADC-Based TDC

Authors: Zule Xu, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

A 25 3 μW at 60 fps 240 × 160 Pixel Vision Sensor for Motion Capturing With In-Pixel Nonvolatile Analog Memory Using CAAC-IGZO FET

Authors: Takuro Ohmaru, Takashi Nakagawa, Shuhei Maeda, Yuki Okamoto, Munehiro Kozuma, Seiichi Yoneda, Hiroki Inoue, Yoshiyuki Kurokawa, Takayuki Ikeda, Yoshinori Ieda, Naoto Yamade, Hidekazu Miyairi, Makoto Ikeda, Shunpei Yamazaki

Reset-Check-Reverse-Flag Scheme on NRAM With 50% Bit Error Rate or 35% Parity Overhead and 16% Decoding Latency Reductions for Read-Intensive Storage Class Memory

Authors: Sheyang Ning, Tomoko Ogura Iwasaki, Shuhei Tanakamaru, Darlene Viviani, Henry Huang, Monte Manning, Thomas Rueckes, Ken Takeuchi

A Fractional-N Sub-Sampling PLL using a Pipelined Phase-Interpolator With an FoM of -250 dB

Authors: Aravind Tharayil Narayanan, Makihiko Katsuragi, Kento Kimura, Satoshi Kondo, Korkut Kaan Tokgoz, Kengo Nakata, Wei Deng, Kenichi Okada, Akira Matsuzawa

A 2.2 GHz -242dB-FOM 4.2 mW ADC-PLL Using Digital Sub-Sampling Architecture

Authors: Teerachot Siriburanon, Satoshi Kondo, Kento Kimura, Tomohiro Ueno, Satoshi Kawashima, Tohru Kaneko, Wei Deng, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

A Low-Power Low-Noise mm-Wave Subsampling PLL Using Dual-Step-Mixing ILFD and Tail-Coupling Quadrature Injection-Locked Oscillator for IEEE 802.11ad

Authors: Teerachot Siriburanon, Satoshi Kondo, Makihiko Katsuragi, Hanli Liu, Kento Kimura, Wei Deng, Kenichi Okada, Akira Matsuzawa

An Inductively Powered Wireless Solid-State Drive System With Merged Error Correction of High-Speed Wireless Data Links and NAND Flash Memories

Authors: Atsutake Kosuge, Junki Hashiba, Toru Kawajiri, So Hasegawa, Tsunaaki Shidei, Hiroki Ishikuro, Tadahiro Kuroda, Ken Takeuchi

A Compact First-Order ΣΔ Modulator for Analog High-Volume Testing of Complex System-on-Chips in a 14 nm Tri-Gate Digital CMOS Process

Authors: Takao Oshita, Joseph Shor, David E. Duarte, Avner Kornfeld, George L. Geannopoulos, Jonathan Douglas, Nasser A. Kurd

A Low Power 64 Gb MLC NAND-Flash Memory in 15 nm CMOS Technology

Authors: Mario Sako, Yoshihisa Watanabe, Takao Nakajima, Jumpei Sato, Kazuyoshi Muraoka, Masaki Fujiu, Fumihiro Kono, Michio Nakagawa, Masami Masuda, Koji Kato, Yuri Terada, Yuki Shimizu, Mitsuaki Honma, Akihiro Imamoto, Tomoko Araya, Hayato Konno, Takuya Okanaga, Tomofumi Fujimura, Xiaoqing Wang, Mai Muramoto, Masahiro Kamoshida, Masatoshi Kohno, Yoshinao Suzuki, Tomoharu Hashiguchi, Tsukasa Kobayashi, Masashi Yamaoka, Ryuji Yamashita

A 28 nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macro for Automotive Achieving 6.4 GB/s Read Throughput by 200 MHz No-Wait Read Operation and 2.0 MB/s Write Throughput at Tj of 170°C

Authors: Yasuhiko Taito, Takashi Kono, Masaya Nakano, Tomoya Saito, Takashi Ito, Kenji Noguchi, Hideto Hidaka, Tadaaki Yamauchi

A 20k-Spin Ising Chip to Solve Combinatorial Optimization Problems With CMOS Annealing

Authors: Masanao Yamaoka, Chihiro Yoshimura, Masato Hayashi, Takuya Okuyama, Hidetaka Aoki, Hiroyuki Mizuno

A 14 nm 1.1 Mb Embedded DRAM Macro With 1 ns Access

Authors: Gregory Fredeman, Donald W. Plass, Abraham Mathews, Janakiraman Viraraghavan, Kenneth Reyer, Thomas J. Knips, Thomas Miller, Elizabeth L. Gerhard, Dinesh Kannambadi, Chris Paone, Dongho Lee, Daniel Rainey, Michael A. Sperling, Michael Whalen, Steven Burns, Rajesh Reddy Tummuru, Herbert Ho, Alberto Cestero, Norbert Arnold, Babar Khan, Toshiaki Kirihata, Subramanian S. Iyer

A 10 ps Time-Resolution CMOS Image Sensor With Two-Tap True-CDS Lock-In Pixels for Fluorescence Lifetime Imaging

Authors: Min-Woong Seo, Keiichiro Kagawa, Keita Yasutomi, Yoshimasa Kawata, Nobukazu Teranishi, Zhuo Li, Izhal Abdul Halin, Shoji Kawahito

Introduction to the January Special Issue on the 2015 IEEE International Solid-State Circuits Conference

Authors: Edith Beign, Jinuk Luke Shin, Yusuke Oike, Chulwoo Kim, Jan Genoe

Jussi Ryynnen Introduction to the December Special Issue on the 2015 IEEE International Solid-State Circuits Conference

Authors: Makoto Takamiya, Jieh-Tsorng Wu, Jussi Ryynnen, Kenichi Okada, Jaeha Kim

RF-Powered Transceiver With an Energy- and Spectral-Efficient IF-Based Quadrature Backscattering Transmitter

Authors: Atsushi Shirane, Yiming Fang, Haowei Tan, Taiki Ibe, Hiroyuki Ito, Noboru Ishihara, Kazuya Masu

A 28 Gb/s Multistandard Serial Link Transceiver for Backplane Applications in 28 nm CMOS

Authors: Bo Zhang, Karapet Khanoyan, Hamid Hatamkhani, Haitao Tong, Kangmin Hu, Siavash Fallahi, Mohammed M. Abdul-Latif, Kambiz Vakilian, Ichiro Fujimori, Anthony Brewster

Wide-Supply-Range All-Digital Leakage Variation Sensor for On-Chip Process and Temperature Monitoring

Authors: Islam A. K. M. Mahfuzul, Jun Shiomi, Tohru Ishihara, Hidetoshi Onodera

A 1 mm Pitch 80 80 Channel 322 Hz Frame-Rate Multitouch Distribution Sensor With Two-Step Dual-Mode Capacitance Scan

Authors: Noriyuki Miura, Shiro Dosho, Hiroyuki Tezuka, Takuji Miki, Daisuke Fujimoto, Takuya Kiriyama, Makoto Nagata

A Reference-Less Single-Loop Half-Rate Binary CDR

Authors: Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura

Normally-Off Computing for Crystalline Oxide Semiconductor-Based Multicontext FPGA Capable of Fine-Grained Power Gating on Programmable Logic Element With Nonvolatile Shadow Register

Authors: Takeshi Aoki, Yuki Okamoto, Takashi Nakagawa, Munehiro Kozuma, Yoshiyuki Kurokawa, Takayuki Ikeda, Naoto Yamade, Yutaka Okazaki, Hidekazu Miyairi, Masahiro Fujita, Jun Koyama, Shunpei Yamazaki

A 60 dB SNDR 35 MS/s SAR ADC With Comparator-Noise-Based Stochastic Residue Estimation

Authors: Bob Verbruggen, Jorgo Tsouhlarakis, Takaya Yamamoto, Masao Iriguchi, Ewout Martens, Jan Craninckx

A 4.2 mW 50 MS/s 13 bit CMOS SAR ADC With SNR and SFDR Enhancement Techniques

Authors: Takuji Miki, Takashi Morie, Kazuo Matsukawa, Yoji Bando, Takeshi Okumoto, Koji Obata, Shiro Sakiyama, Shiro Dosho

An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers

Authors: James Lin, Daehwa Paik, Seungjong Lee, Masaya Miyahara, Akira Matsuzawa

Design of A Transformer-Based Reconfigurable Digital Polar Doherty Power Amplifier Fully Integrated in Bulk CMOS

Authors: Song Hu, Shouhei Kousai, Jong Seok Park, Outmane Lemtiri Chlieh, Hua Wang

Highly Reliable Reference Bitline Bias Designs for 64 Mb and 128 Mb Chain FeRAMs

Authors: Ryu Ogiwara, Daisaburo Takashima, Sumiko Doumae, Shinichiro Shiratake, Ryosuke Takizawa, Hidehiro Shiga

A 3.7 M-Pixel 1300-fps CMOS Image Sensor With 5.0 G-Pixel/s High-Speed Readout Circuit

Authors: Shunsuke Okura, Osamu Nishikido, Yusuke Sadanaga, Yasuhiro Kosaka, Norihiko Araki, Kazuhiro Ueda, Fukashi Morishita

Dynamic Architecture and Frequency Scaling in 0.8-1.2 GS/s 7 b Subranging ADC

Authors: Kentaro Yoshioka, Ryo Saito, Takumi Danjo, Sanroku Tsukamoto, Hiroki Ishikuro

A 2.7 GHz to 7 GHz Fractional-N LC-PLL Utilizing Multi-Metal Layer SoC Technology in 28 nm CMOS

Authors: Chang-Hyeon Lee, Lindel Kabalican, Yan Ge, Hendra Kwantono, Greg Unruh, Mark Chambers, Ichiro Fujimori

On-Chip Measurement of Clock and Data Jitter With Sub-Picosecond Accuracy for 10 Gb/s Multilane CDRs

Authors: Joshua Liang, Mohammad Sadegh Jalali, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura

Compact BJT-Based Thermal Sensor for Processor Applications in a 14 nm tri-Gate CMOS Process

Authors: Takao Oshita, Joseph Shor, David E. Duarte, Avner Kornfeld, Dror Zilberman

Correction to "A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range"

Authors: Badr Malki, Takaya Yamamoto, Bob Verbruggen, Piet Wambacq, Jan Craninckx

Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction

Authors: Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu

Integrated Line Driver for Digital Pulse-Width Modulation Driven AMOLED Displays on Flex

Authors: Jan Genoe, Koji Obata, Marc Ameys, Kris Myny, Tung Huei Ke, Manoj Nag, Soeren Steudel, Sarah Schols, Joris Maas, Ashutosh Tripathi, Jan-Laurens P. J. van der Steen, Tim Ellis, Gerwin H. Gelinck, Paul Heremans

A Fully Synthesizable All-Digital PLL With Interpolative Phase Coupled Oscillator, Current-Output DAC, and Fine-Resolution Digital Varactor Using Gated Edge Injection Technique

Authors: Wei Deng, Dongsheng Yang, Tomohiro Ueno, Teerachot Siriburanon, Satoshi Kondo, Kenichi Okada, Akira Matsuzawa

A 28 nm High-k/MG Heterogeneous Multi-Core Mobile Application Processor With 2 GHz Cores and Low-Power 1 GHz Cores

Authors: Mitsuhiko Igarashi, Toshifumi Uemura, Ryo Mori, Hiroshi Kishibe, Midori Nagayama, Masaaki Taniguchi, Kohei Wakahara, Toshiharu Saito, Masaki Fujigaya, Kazuki Fukuoka, Koji Nii, Takeshi Kataoka, Toshihiro Hattori

A 1 Gb 2 GHz 128 GB/s Bandwidth Embedded DRAM in 22 nm Tri-Gate CMOS Technology

Authors: Fatih Hamzaoglu, Umut Arslan, Nabhendra Bisnik, Swaroop Ghosh, Manoj B. Lal, Nick Lindert, Mesut Meterelliyoz, Randy B. Osborne, Joodong Park, Shigeki Tomishima, Yih Wang, Kevin Zhang

A 28 Gb/s 560 mW Multi-Standard SerDes With Single-Stage Analog Front-End and 14-Tap Decision Feedback Equalizer in 28 nm CMOS

Authors: Hiroshi Kimura, Pervez M. Aziz, Tai Jing, Ashutosh Sinha, Shiva Prasad Kotagiri, Ram Narayan, Hairong Gao, Ping Jing, Gary Hom, Anshi Liang, Eric Zhang, Aniket Kadkol, Ruchi Kothari, Gordon Chan, Yehui Sun, Benjamin Ge, Jason Zeng, Kathy Ling, Michael C. Wang, Amaresh V. Malipatil, Lijun Li, Christopher J. Abel, Freeman Zhong

Polar Antenna Impedance Detection and Tuning for Efficiency Improvement in a 3G/4G CMOS Power Amplifier

Authors: Shouhei Kousai, Kohei Onizuka, Junji Wadatsumi, Takashi Yamaguchi, Yasuhiko Kuriyama, Masami Nagaoka

A Full-Duplex Line Driver for Gigabit Ethernet With Rail-to-Rail Class-AB Output Stage in 28 nm CMOS

Authors: Hui Pan, Yuan Yao, Mostafa Hammad, Junhua Tan, Karim Abdelhalim, Evelyn Wenting Wang, Rick C. J. Hsu, Derek Tam, Ichiro Fujimori

A 1.95 GHz Fully Integrated Envelope Elimination and Restoration CMOS Power Amplifier Using Timing Alignment Technique for WCDMA and LTE

Authors: Kazuaki Oishi, Eiji Yoshida, Yasufumi Sakai, Hideki Takauchi, Yoichi Kawano, Noriaki Shirai, Hideki Kano, Masahiro Kudo, Tomotoshi Murakami, Tetsuro Tamura, Shigeaki Kawai, Kazuo Suto, Hiroshi Yamazaki, Toshihiko Mori

Introduction to the Special Issue on the 2014 IEEE International Solid-State Circuits Conference (ISSCC)

Authors: Makoto Nagata, Lucien J. Breems, Carlo Samori, Sven Mattisson, Pavan Kumar Hanumolu

A Fully Integrated SAR ADC Using Digital Correction Technique for Triple-Mode Mobile Transceiver

Authors: Hideo Nakane, Ryuichi Ujiie, Takashi Oshima, Takaya Yamamoto, Keisuke Kimura, Yuichi Okuda, Kosuke Tsuiji, Tatsuji Matsuura

A 0.6 V Input CCM/DCM Operating Digital Buck Converter in 40 nm CMOS

Authors: Xin Zhang, Po-Hung Chen, Yasuyuki Okuma, Koichi Ishida, Yoshikatsu Ryu, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya

A Fully Static Topologically-Compressed 21-Transistor Flip-Flop With 75% Power Saving

Authors: Natsumi Kawai, Shinichi Takayama, Junya Masumi, Naoto Kikuchi, Yasuo Itoh, Kyosuke Ogawa, Akimitsu Ugawa, Hiroaki Suzuki, Yasunori Tanaka

A 25-to-28 Gb/s High-Sensitivity (-9.7 dBm) 65 nm CMOS Optical Receiver for Board-to-Board Interconnects

Authors: Takashi Takemoto, Hiroki Yamashita, Toru Yazaki, Norio Chujo, Yong Lee, Yasunobu Matsuoka

A 12 Bit 1.6 GS/s BiCMOS 22 Hierarchical Time-Interleaved Pipeline ADC

Authors: Manar El-Chammas, Xiaopeng Li, Shigenobu Kimura, Kenneth Maclean, Jake Hu, Mark Weaver, Matthew Gindlesperger, Scott Kaylor, Robert Payne, Charles K. Sestok, William Bright

A Wearable 8-Channel Active-Electrode EEG/ETI Acquisition System for Body Area Networks

Authors: Jiawei Xu, Srinjoy Mitra, Akinori Matsumoto, Shrishail Patki, Chris Van Hoof, Kofi A. A. Makinwa, Refet Firat Yazicioglu

A 70 dB DR 10 b 0-to-80 MS/s Current-Integrating SAR ADC With Adaptive Dynamic Range

Authors: Badr Malki, Takaya Yamamoto, Bob Verbruggen, Piet Wambacq, Jan Craninckx

1 Mb 0.41 m2 2T-2R Cell Nonvolatile TCAM With Two-Bit Encoding and Clocked Self-Referenced Sensing

Authors: Jing Li, Robert K. Montoye, Masatoshi Ishii, Leland Chang

A 6-bit, 1-GS/s, 9.9-mW, Interpolated Subranging ADC in 65-nm CMOS

Authors: Takumi Danjo, Masato Yoshioka, Masayuki Isogai, Masanori Hoshino, Sanroku Tsukamoto

A 25-Gb/s 2.2-W 65-nm CMOS Optical Transceiver Using a Power-Supply-Variation-Tolerant Analog Front End and Data-Format Conversion

Authors: Takashi Takemoto, Hiroki Yamashita, Fumio Yuki, Noboru Masuda, Hidehiro Toyoda, Norio Chujo, Yong Lee, Shinji Tsuji, Shinji Nishimura

A 14b 60 MS/s Pipelined ADC Adaptively Cancelling Opamp Gain and Nonlinearity

Authors: Yuichi Miyahara, Mitsuhiro Sano, Kazuo Koyama, Toshikazu Suzuki, Koichi Hamashita, Bang-Sup Song

A Compact, Low-Power and Low-Jitter Dual-Loop Injection Locked PLL Using All-Digital PVT Calibration

Authors: Ahmed Musa, Wei Deng, Teerachot Siriburanon, Masaya Miyahara, Kenichi Okada, Akira Matsuzawa

40-nm Embedded Split-Gate MONOS (SG-MONOS) Flash Macros for Automotive With 160-MHz Random Access for Code and Endurance Over 10 M Cycles for Data at the Junction Temperature of 170°C

Authors: Takashi Kono, Takashi Ito, Tamaki Tsuruda, Takayuki Nishiyama, Tsutomu Nagasawa, Tomoya Ogawa, Yoshiyuki Kawashima, Hideto Hidaka, Tadaaki Yamauchi

An LDPC Decoder With Time-Domain Analog and Digital Mixed-Signal Processing

Authors: Daisuke Miyashita, Ryo Yamaki, Kazunori Hashiyoshi, Hiroyuki Kobayashi, Shouhei Kousai, Yukihito Oowaki, Yasuo Unekawa

A 130.7-mm2 2-Layer 32-Gb ReRAM Memory Device in 24-nm Technology

Authors: Tz-Yi Liu, Tian Hong Yan, Roy Scheuerlein, Yingchang Chen, Jeffrey KoonYee Lee, Gopinath Balakrishnan, Gordon Yee, Henry Zhang, Alex Yap, Jingwen Ouyang, Takahiko Sasaki, Ali Al-Shamma, Chin-Yu Chen, Mayank Gupta, Greg Hilton, Achal Kathuria, Vincent Lai, Masahide Matsumoto, Anurag Nigam, Anil Pai, Jayesh Pakhale, Chang Hua Siau, Xiaoxia Wu, Yibo Yin, Nicolas Nagel, Yoichiro Tanaka, Masaaki Higashitani, Tim Minvielle, Chandu Gorla, Takayuki Tsukamoto, Takeshi Yamaguchi, Mutsumi Okajima, Takayuki Okamura, Satoru Takase, Hirofumi Inoue, Luca Fasoli

A 0.15-mm-Thick Noncontact Connector for MIPI Using a Vertical Directional Coupler

Authors: Atsutake Kosuge, Wataru Mizuhara, Tsunaaki Shidei, Tsutomu Takeya, Noriyuki Miura, Masao Taguchi, Hiroki Ishikuro, Tadahiro Kuroda

The 10th Generation 16-Core SPARC64™ Processor for Mission Critical UNIX Server

Authors: Ryuji Kan, Tomohiro Tanaka, Go Sugizaki, Kinya Ishizaka, Ryuichi Nishiyama, Sota Sakabayashi, Yoichi Koyanagi, Ryuji Iwatsuki, Kazumi Hayasaka, Taiki Uemura, Gaku Ito, Yoshitomo Ozeki, Hiroyuki Adachi, Kazuhiro Furuya, Tsuyoshi Motokurumada

A 27% Active and 85% Standby Power Reduction in Dual-Power-Supply SRAM Using BL Power Calculator and Digitally Controllable Retention Circuit

Authors: Fumihiko Tachibana, Osamu Hirabayashi, Yasuhisa Takeyama, Miyako Shizuno, Atsushi Kawasumi, Keiichi Kushida, Azuma Suzuki, Yusuke Niki, Shinichi Sasaki, Tomoaki Yabe, Yasuo Unekawa

A 0.18-m CMOS SoC for a 100-m-Range 10-Frame/s 200 96-Pixel Time-of-Flight Depth Sensor

Authors: Cristiano Niclass, Mineki Soga, Hiroyuki Matsubara, Masaru Ogawa, Manabu Kagami

Highlights of the ISSCC 2013 Processors and High Performance Digital Sessions

Authors: Timothy Fischer, Byeong-Gyu Nam, Leland Chang, Tadahiro Kuroda, Michiel A. P. Pertijs

A High Voltage Self-Biased Integrated DC-DC Buck Converter With Fully Analog MPPT Algorithm for Electrostatic Energy Harvesters

Authors: Stefano Stanzione, Chris van Liempd, Rob van Schaijk, Yasuyuki Naito, Refet Firat Yazicioglu, Chris Van Hoof

Design of a 300-mV 2.4-GHz Receiver Using Transformer-Coupled Techniques

Authors: Fan Zhang, Yasunori Miyahara, Brian P. Otis

A Blind Baud-Rate ADC-Based CDR

Authors: Clifford Ting, Joshua Liang, Ali Sheikholeslami, Masaya Kibune, Hirotaka Tamura

A Fully Integrated 60-GHz CMOS Transceiver Chipset Based on WiGig/IEEE 802.11ad With Built-In Self Calibration for Mobile Usage

Authors: Noriaki Saito, Takayuki Tsukizawa, Naganori Shirakata, Tadashi Morita, Koichiro Tanaka, Junji Sato, Yohei Morishita, Masaki Kanemaru, Ryo Kitamura, Takahiro Shima, Toshifumi Nakatani, Kenji Miyanaga, Tomoya Urushihara, Hiroyuki Yoshikawa, Takenori Sakamoto, Hiroyuki Motozuka, Yoshinori Shirakawa, Naoya Yosoku, Akira Yamamoto, Ryosuke Shiozaki, Koji Takinami

A 32 Gb/s Data-Interpolator Receiver With Two-Tap DFE Fabricated With 28-nm CMOS Process

Authors: Yoshiyasu Doi, Takayuki Shibasaki, Takumi Danjo, Win Chaivipas, Takushi Hashida, Hiroki Miyaoka, Masanori Hoshino, Yoichi Koyanagi, Takuji Yamamoto, Sanroku Tsukamoto, Hirotaka Tamura

A 14b 80 MS/s SAR ADC With 73.6 dB SNDR in 65 nm CMOS

Authors: Ron Kapusta, Junhua Shen, Steven Decker, Hongxing Li, Eitake Ibaragi, Haiyang Zhu

A 250-MHz 18-Mb Full Ternary CAM With Low-Voltage Matchline Sensing Scheme in 65-nm CMOS

Authors: Isamu Hayashi, Teruhiko Amano, Naoya Watanabe, Yuji Yano, Yasuto Kuroda, M. Shirata, Katsumi Dosaka, Koji Nii, Hideyuki Noda, Hiroyuki Kawai

A Self-Authenticating Chip Architecture Using an Intrinsic Fingerprint of Embedded DRAM

Authors: Sami Rosenblatt, Srivatsan Chellappa, Alberto Cestero, Norman Robson, Toshiaki Kirihata, Subramanian S. Iyer

Low-Power On-Chip Charge-Recycling DC-DC Conversion Circuit and System

Authors: Kazuhiro Ueda, Fukashi Morishita, Shunsuke Okura, Leona Okamura, Tsutomu Yoshihara, Kazutami Arimoto

Active Terahertz Imaging Using Schottky Diodes in CMOS: Array and 860-GHz Pixel

Authors: Ruonan Han, Yaming Zhang, Youngwan Kim, Dae Yeon Kim, Hisashi Shichijo, Ehsan Afshari, Kenneth K. O

A Sub-0.3 V Area-Efficient L-Shaped 7T SRAM With Read Bitline Swing Expansion Schemes Based on Boosted Read-Bitline, Asymmetric-VTH Read-Port, and Offset Cell VDD Biasing Techniques

Authors: Meng-Fan Chang, Ming-Bin Chen, Lai-Fu Chen, Shu-Meng Yang, Yao-Jen Kuo, Jui-Jen Wu, Hsiu-Yun Su, Yuan-Hua Chu, Wen-Chin Wu, Tzu-Yi Yang, Hiroyuki Yamauchi

98 mW 10 Gbps Wireless Transceiver Chipset With D-Band CMOS Circuits

Authors: Minoru Fujishima, Mizuki Motoyoshi, Kosuke Katayama, Kyoya Takano, Naoko Ono, Ryuichi Fujimoto

0.5 V Start-Up 87% Efficiency 0.75 mm2 On-Chip Feed-Forward Single-Inductor Dual-Output (SIDO) Boost DC-DC Converter for Battery and Solar Cell Operation Sensor Network Micro-Computer Integration

Authors: Yasunobu Nakase, Shinichi Hirose, Hiroshi Onoda, Yasuhiro Ido, Yoshiaki Shimizu, Tsukasa Oishi, Toshio Kumamoto, Toru Shimizu

Increase of Crosstalk Noise Due to Imbalanced Threshold Voltage Between nMOS and pMOS in Subthreshold Logic Circuits

Authors: Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai

Correction to "A 2 Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60 GHz Short-Range Wireless Communication"

Authors: Toshiya Mitomo, Yukako Tsutsumi, Hiroaki Hoshino, Masahiro Hosoya, Tong Wang, Yuta Tsubouchi, Ryoichi Tachibana, Akihide Sai, Yuka Kobayashi, Daisuke Kurose, Tomohiko Ito, Koichiro Ban, Tomoya Tandai, Takeshi Tomizawa

A 0.41 A Standby Leakage 32 kb Embedded SRAM with Low-Voltage Resume-Standby Utilizing All Digital Current Comparator in 28 nm HKMG CMOS

Authors: Noriaki Maeda, Shigenobu Komatsu, Masao Morimoto, Koji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yasuhisa Shimazaki

Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges

Authors: Shinji Miyano, Shinichi Moriwaki, Yasue Yamamoto, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Hirofumi Shinohara

Field Tolerant Dynamic Intrinsic Chip ID Using 32 nm High-K/Metal Gate SOI Embedded DRAM

Authors: Sami Rosenblatt, Daniel Fainstein, Alberto Cestero, John Safran, Norman Robson, Toshiaki Kirihata, Subramanian S. Iyer

A 12-Gb/s Non-Contact Interface With Coupled Transmission Lines

Authors: Tsutomu Takeya, Lan Nan, Shinya Nakano, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda

An Offset-Tolerant Fast-Random-Read Current-Sampling-Based Sense Amplifier for Small-Cell-Current Nonvolatile Memory

Authors: Meng-Fan Chang, Shin-Jang Shen, Chia-Chi Liu, Che-Wei Wu, Yu-Fan Lin, Ya-Chin King, Chorng-Jung Lin, Hung-Jen Liao, Yu-Der Chih, Hiroyuki Yamauchi

A 0.4-mW/Gb/s Near-Ground Receiver Front-End With Replica Transconductance Termination Calibration for a 16-Gb/s Source-Series Terminated Transceiver

Authors: Kambiz Kaviani, Amir Amirkhany, Charlie Huang, Phuong Le, Wendemagegnehu T. Beyene, Chris J. Madden, Keisuke Saito, Koji Sano, Vinod Inipodu Murugan, Kun-Yung Ken Chang, Xingchao Chuck Yuan

Low-Voltage Embedded NAND-ROM Macros Using Data-Aware Sensing Reference Scheme for VDDmin, Speed and Power Improvement

Authors: Shu-Meng Yang, Meng-Fan Chang, Chi-Chuang Chiang, Ming-Bin Chen, Hiroyuki Yamauchi

A 100-m Range 10-Frame/s 340,x,96-Pixel Time-of-Flight Depth Sensor in 0.18-m CMOS

Authors: Cristiano Niclass, Mineki Soga, Hiroyuki Matsubara, Satoru Kato, Manabu Kagami

A 32 nm SoC With Dual Core ATOM Processor and RF WiFi Transceiver

Authors: Hasnain Lakdawala, Mark Schaecher, Chang-Tsung Fu, Rahul Dilip Limaye, Jon Duster, Yulin Tan, Ajay Balankutty, Erkan Alpman, Chun C. Lee, Khoa Minh Nguyen, Hyung-Jin Lee, Ashoke Ravi, Satoshi Suzuki, Brent R. Carlton, Hyung Seok Kim, Marian Verhelst, Stefano Pellerano, Tong Kim, Satish Venkatesan, Durgesh Srivastava, Peter Vandervoorn, Jad Rizk, Chia-Hong Jan, Sunder Ramamurthy, Raj Yavatkar, Krishnamurthy Soumyanath

Insole Pedometer With Piezoelectric Energy Harvester and 2 V Organic Circuits

Authors: Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Yasuhiro Shinozuka, Hiroshi Fuketa, Tomoyuki Yokota, Ute Zschieschang, Hagen Klauk, Gregory Tortissier, Tsuyoshi Sekitani, Hiroshi Toshiyoshi, Makoto Takamiya, Takao Someya, Takayasu Sakurai

A 19 nm 112.8 mm2 64 Gb Multi-Level Flash Memory With 400 Mbit/sec/pin 1.8 V Toggle Mode Interface

Authors: Kazushige Kanda, Noboru Shibata, Toshiki Hisada, Katsuaki Isobe, Manabu Sato, Yui Shimizu, Takahiro Shimizu, Takahiro Sugimoto, Tomohiro Kobayashi, Naoaki Kanagawa, Yasuyuki Kajitani, Takeshi Ogawa, Kiyoaki Iwasa, Masatsugu Kojima, Toshihiro Suzuki, Yuya Suzuki, Shintaro Sakai, Tomofumi Fujimura, Yuko Utsunomiya, Toshifumi Hashimoto, Naoki Kobayashi, Yuuki Matsumoto, Satoshi Inoue, Yoshinao Suzuki, Yasuhiko Honda, Yosuke Kato, Shingo Zaitsu, Hardwell Chibvongodze, Mitsuyuki Watanabe, Hong Ding, Naoki Ookuma, Ryuji Yamashita

Full Four-Channel 6.3-Gb/s 60-GHz CMOS Transceiver With Low-Power Analog and Digital Baseband Circuitry

Authors: Kenichi Okada, Keitarou Kondou, Masaya Miyahara, Masashi Shinagawa, Hiroki Asada, Ryo Minami, Tatsuya Yamaguchi, Ahmed Musa, Yuuki Tsukui, Yasuo Asakura, Shinya Tamonoki, Hiroyuki Yamagishi, Yasufumi Hino, Takahiro Sato, Hironori Sakaguchi, Naoki Shimasaki, Toshihiko Ito, Yasuaki Takeuchi, Ning Li, Qinghong Bu, Rui Murakami, Keigo Bunsen, Kota Matsushita, Makoto Noda, Akira Matsuzawa

A Global-Shutter CMOS Image Sensor With Readout Speed of 1-Tpixel/s Burst and 780-Mpixel/s Continuous

Authors: Yasuhisa Tochigi, Katsuhiko Hanzawa, Yuri Kato, Rihito Kuroda, Hideki Mutoh, Ryuta Hirose, Hideki Tominaga, Kenji Takubo, Yasushi Kondo, Shigetoshi Sugawa

Introduction to the Special Issue on the 2012 IEEE International Solid-State Circuits Conference

Authors: Maurits Ortmanns, Timothy Fischer, Uming Ko, Wim Dehaene, Yasuhiro Takai

An 8 Mb Multi-Layered Cross-Point ReRAM Macro With 443 MB/s Write Throughput

Authors: Akifumi Kawahara, Ryotaro Azuma, Yuuichirou Ikeda, Ken Kawai, Yoshikazu Katoh, Yukio Hayakawa, Kiyotaka Tsuji, Shinichi Yoneda, Atsushi Himeno, Kazuhiko Shimakawa, Takeshi Takagi, Takumi Mikawa, Kunitoshi Aono

A 4.1-pJ/b, 16-Gb/s Coded Differential Bidirectional Parallel Electrical Link

Authors: Amir Amirkhany, Kambiz Kaviani, Ali-Azam Abbasfar, H. Md. Shuaeb Fazeel, Wendemagegnehu T. Beyene, Chikara Hoshino, Chris J. Madden, Ken Chang, Chuck Yuan

Ring Amplifiers for Switched Capacitor Circuits

Authors: Benjamin P. Hershberg, Skyler Weaver, Kazuki Sobue, Seiji Takeuchi, Koichi Hamashita, Un-Ku Moon

A 28.3 mW PA-Closed Loop for Linearity and Efficiency Improvement Integrated in a + 27.1 dBm WCDMA CMOS Power Amplifier

Authors: Shouhei Kousai, Kohei Onizuka, Takashi Yamaguchi, Yasuhiko Kuriyama, Masami Nagaoka

A DC-to-1 GHz Tunable RF Delta Sigma ADC Achieving DR = 74 dB and BW = 150 MHz at f0 = 450 MHz Using 550 mW

Authors: Hajime Shibata, Richard Schreier, Wenhua Yang, Ali Shaikh, Donald Paterson, Trevor C. Caldwell, David Alldred, Ping Wing Lai

A 2-Gb/s Throughput CMOS Transceiver Chipset With In-Package Antenna for 60-GHz Short-Range Wireless Communication

Authors: Toshiya Mitomo, Yukako Tsutsumi, Hiroaki Hoshino, Masahiro Hosoya, Tong Wang, Yuta Tsubouchi, Ryoichi Tachibana, Akihide Sai, Yuka Kobayashi, Daisuke Kurose, Tomohiko Ito, Koichiro Ban, Tomoya Tandai, Takeshi Tomizawa

1-W 3.3-16.3-V Boosting Wireless Power Transfer Circuits With Vector Summing Power Controller

Authors: Kazutoshi Tomita, Ryota Shinoda, Tadahiro Kuroda, Hiroki Ishikuro

An 80 mV Startup Dual-Mode Boost Converter by Charge-Pumped Pulse Generator and Threshold Voltage Tuned Oscillator With Hot Carrier Injection

Authors: Po-Hung Chen, Xin Zhang, Koichi Ishida, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai

CMOS Circuits to Measure Timing Jitter Using a Self-Referenced Clock and a Cascaded Time Difference Amplifier With Duty-Cycle Compensation

Authors: Kiichi Niitsu, Masato Sakurai, Naohiro Harigai, Takahiro J. Yamaguchi, Haruo Kobayashi

Rotary Coding for Power Reduction and S/N Improvement in Inductive-Coupling Data Communication

Authors: Andrzej Radecki, Noriyuki Miura, Hiroki Ishikuro, Tadahiro Kuroda

Compact, High Impedance and Wide Bandwidth Detectors for Characterization of Millimeter Wave Performance

Authors: Chikuang Yu, Chieh-Lin Wu, Sandeep Kshattry, Yang-Hun Yun, Choong-Yul Cha, Hisashi Shichijo, Kenneth K. O

Simultaneous 6-Gb/s Data and 10-mW Power Transmission Using Nested Clover Coils for Noncontact Memory Card

Authors: Andrzej Radecki, Yuxiang Yuan, Noriyuki Miura, Iori Aikawa, Yasuhiro Take, Hiroki Ishikuro, Tadahiro Kuroda

Nonvolatile Memory With Extremely Low-Leakage Indium-Gallium-Zinc-Oxide Thin-Film Transistor

Authors: Hiroki Inoue, Takanori Matsuzaki, Shuhei Nagatsuka, Yutaka Okazaki, Toshinari Sasaki, Kousei Noda, Daisuke Matsubayashi, Takahiko Ishizu, Tatsuya Onuki, Atsuo Isobe, Yutaka Shionoiri, Kiyoshi Kato, Takashi Okuda, Jun Koyama, Shunpei Yamazaki

A 1.9 GHz CMOS Power Amplifier With Embedded Linearizer to Compensate AM-PM Distortion

Authors: Kohei Onizuka, Hiroaki Ishihara, Masahiro Hosoya, Shigehito Saigusa, Osamu Watanabe, Shoji Otaka

A 1-1-1-1 MASH Delta-Sigma Modulator With Dynamic Comparator-Based OTAs

Authors: Kentaro Yamamoto and Anthony Chan Carusone

A Low-Power Level Shifter With Logic Error Correction for Extremely Low-Voltage Digital CMOS LSIs

Authors: Yuji Osaki, Tetsuya Hirose, Nobutaka Kuroki, Masahiro Numa

A Time-Resolved, Low-Noise Single-Photon Image Sensor Fabricated in Deep-Submicron CMOS Technology

Authors: Marek Gersbach, Yuki Maruyama, Rahmadi Trimananda, Matthew W. Fishburn, David Stoppa, Justin A. Richardson, Richard Walker, Robert K. Henderson, Edoardo Charbon

Associative Memory for Nearest-Hamming-Distance Search Based on Frequency Mapping

Authors: Hans Jrgen Mattausch, Wataru Imafuku, Akio Kawabata, Tania Ansari, Masahiro Yasuda, Tetsushi Koide

A 30-MHz-2.4-GHz CMOS Receiver With Integrated RF Filter and Dynamic-Range-Scalable Energy Detector for Cognitive Radio Systems

Authors: Masaki Kitsunezuka, Hiroshi Kodama, Naoki Oshima, Kazuaki Kunihiro, Tadashi Maeda, Muneo Fukaishi

Startup Techniques for 95 mV Step-Up Converter by Capacitor Pass-On Scheme and VTH-Tuned Oscillator With Fixed Charge Programming

Authors: Po-Hung Chen, Koichi Ishida, Katsuyuki Ikeuchi, Xin Zhang, Kentaro Honda, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai

A 10-Bit 80-MS/s Decision-Select Successive Approximation TDC in 65-nm CMOS

Authors: Hayun Chung, Hiroki Ishikuro, Tadahiro Kuroda

A 0.5 V 1.1 MS/sec 6.3 fJ/Conversion-Step SAR-ADC With Tri-Level Comparator in 40 nm CMOS

Authors: Akira Shikata, Ryota Sekimoto, Tadahiro Kuroda, Hiroki Ishikuro

A Tri-Modal 20-Gbps/Link Differential/DDR3/GDDR5 Memory Interface

Authors: Kambiz Kaviani, Ting Wu, Jason Wei, Amir Amirkhany, Jie Shen, T. J. Chin, Chintan Thakkar, Wendemagegnehu T. Beyene, Norman Chan, Catherine Chen, Bing Ren Chuang, Deborah Dressler, Vijay P. Gadde, Mohammad Hekmat, Eugene Ho, Charlie Huang, Phuong Le, Mahabaleshwara, Chris J. Madden, Navin K. Mishra, Leneesh Raghavan, Keisuke Saito, Ralf Schmitt, Dave Secker, Xudong Shi, H. Md. Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Steve Zhang, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan

A 27% Active-Power-Reduced 40-nm CMOS Multimedia SoC With Adaptive Voltage Scaling Using Distributed Universal Delay Lines

Authors: Yoshifumi Ikenaga, Masahiro Nomura, Shuji Suenaga, Hideo Sonohara, Yoshitaka Horikoshi, Toshiyuki Saito, Yukio Ohdaira, Yoichiro Nishio, Tomohiro Iwashita, Miyuki Satou, Koji Nishida, Koichi Nose, Koichiro Noguchi, Yoshihiro Hayashi, Masayuki Mizuno

A 12.8-Gb/s/link Tri-Modal Single-Ended Memory Interface

Authors: Amir Amirkhany, Jason Wei, Navin K. Mishra, Jie Shen, Wendemagegnehu T. Beyene, Catherine Chen, T. J. Chin, Deborah Dressler, Charlie Huang, Vijay P. Gadde, Mohammad Hekmat, Kambiz Kaviani, Hai Lan, Phuong Le, Mahabaleshwara, Chris J. Madden, Sanku Mukherjee, Leneesh Raghavan, Keisuke Saito, Dave Secker, Arul Sendhil, Ralf Schmitt, H. Md. Shuaeb Fazeel, Gundlapalli Shanmukha Srinivas, Ting Wu, Chanh Tran, Arun Vaidyanath, Kapil Vyas, Ling Yang, Manish Jain, Kun-Yung Ken Chang, Xingchao Yuan

Compact Measurement Schemes for Bit-Line Swing, Sense Amplifier Offset Voltage, and Word-Line Pulse Width to Characterize Sensing Tolerance Margin in a 40 nm Fully Functional Embedded SRAM

Authors: Yen-Huei Chen, Shao-Yu Chou, Quincy Li, Wei-Min Chan, Dar Sun, Hung-Jen Liao, Ping Wang, Meng-Fan Chang, Hiroyuki Yamauchi

An Embedded DRAM Technology for High-Performance NAND Flash Memories

Authors: Daisaburo Takashima, Mitsuhiro Noguchi, Noboru Shibata, Kazushige Kanda, Hiroshi Sukegawa, Shuso Fujii

A 2.5 kV Isolation 35 kV/us CMR 250 Mbps Digital Isolator in Standard CMOS With a Small Transformer Driving Technique

Authors: Shunichi Kaeriyama, Shinichi Uchida, Masayuki Furumiya, Mitsuji Okada, Tadashi Maeda, Masayuki Mizuno

A 100-V AC Energy Meter Integrating 20-V Organic CMOS Digital and Analog Circuits With a Floating Gate for Process Variation Compensation and a 100-V Organic pMOS Rectifier

Authors: Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Tsuyoshi Sekitani, Hiroyoshi Nakajima, Hiroki Maeda, Makoto Takamiya, Takao Someya, Takayasu Sakurai

Introduction to the Special Issue on the 2011 IEEE International Solid-State Circuits Conference

Authors: Alice Wang, Ken Takeuchi, Tanay Karnik, Maysam Ghovanloo, Satoshi Shigematsu

A Low-Noise High Intrascene Dynamic Range CMOS Image Sensor With a 13 to 19b Variable-Resolution Column-Parallel Folding-Integration/Cyclic ADC

Authors: Min-Woong Seo, Sungho Suh, Tetsuya Iida, Taishi Takasawa, Keigo Isobe, Takashi Watanabe, Shinya Itoh, Keita Yasutomi, Shoji Kawahito

Design of the Two-Core x86-64 AMD "Bulldozer" Module in 32 nm SOI CMOS

Authors: Hugh McIntyre, Srikanth Arekapudi, Eric Busta, Timothy Fischer, Michael Golden, Aaron Horiuchi, Tom Meneghini, Samuel Naffziger, James Vinh

A 151-mm2 64-Gb 2 Bit/Cell NAND Flash Memory in 24-nm CMOS Technology

Authors: Koichi Fukuda, Yoshihisa Watanabe, Eiichi Makino, Koichi Kawakami, Jumpei Sato, Teruo Takagiwa, Naoaki Kanagawa, Hitoshi Shiga, Naoya Tokiwa, Yoshihiko Shindo, Takeshi Ogawa, Toshiaki Edahiro, Makoto Iwai, Osamu Nagao, Junji Musha, Takatoshi Minamoto, Yuka Furuta, Kosuke Yanagidaira, Yuya Suzuki, Dai Nakamura, Yoshikazu Hosomura, Rieko Tanaka, Hiromitsu Komai, Mai Muramoto, Go Shikata, Ayako Yuminaka, Kiyofumi Sakurai, Manabu Sakai, Hong Ding, Mitsuyuki Watanabe, Yosuke Kato, Toru Miwa, Alex Mak, Masaru Nakamichi, Gertjan Hemink, Dana Lee, Masaaki Higashitani, Brian Murphy, Bo Lei, Yasuhiko Matsunaga, Kiyomi Naruke, Takahiko Hara

A 1.0625 ~ 14.025 Gb/s Multi-Media Transceiver With Full-Rate Source-Series-Terminated Transmit Driver and Floating-Tap Decision-Feedback Equalizer in 40 nm CMOS

Authors: Freeman Zhong, Shaolei Quan, Wing Liu, Pervez M. Aziz, Tai Jing, Jen Dong, Chintan Desai, Hairong Gao, Monica Garcia, Gary Hom, Tony Huynh, Hiroshi Kimura, Ruchi Kothari, Lijun Li, Cathy Liu, Scott Lowrie, Kathy Ling, Amaresh V. Malipatil, Ram Narayan, Tom Prokop, Chaitanya Palusa, Anil Rajashekara, Ashutosh Sinha, Charlie Zhong, Eric Zhang

A 10: 4 MUX and 4: 10 DEMUX Gearbox LSI for 100-Gigabit Ethernet Link

Authors: Goichi Ono, Keiki Watanabe, Takashi Muto, Hiroki Yamashita, Koji Fukuda, Noboru Masuda, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Fumio Yuki, Masayoshi Yagyu, Hidehiro Toyoda, Masashi Kono, Akihiro Kambe, Seiichi Umai, Tatsuya Saito, Shinji Nishimura

A 60-GHz 16QAM/8PSK/QPSK/BPSK Direct-Conversion Transceiver for IEEE802.15.3c

Authors: Kenichi Okada, Ning Li, Kota Matsushita, Keigo Bunsen, Rui Murakami, Ahmed Musa, Takahiro Sato, Hiroki Asada, Naoki Takayama, Shogo Ito, Win Chaivipas, Ryo Minami, Tatsuya Yamaguchi, Yasuaki Takeuchi, Hiroyuki Yamagishi, Makoto Noda, Akira Matsuzawa

A 12.5+12.5 Gb/s Full-Duplex Plastic Waveguide Interconnect

Authors: Satoshi Fukuda, Yasufumi Hino, Sho Ohashi, Takahiro Takeda, Hiroyuki Yamagishi, Satoru Shinke, Kenji Komori, Masahiro Uno, Yoshiyuki Akiyama, Kenichi Kawasaki, Ali Hajimiri

An Adaptation Engine for a 2x Blind ADC-Based CDR in 65 nm CMOS

Authors: Behrooz Abiri, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune

A 28 nm Dual-Port SRAM Macro With Screening Circuitry Against Write-Read Disturb Failure Issues

Authors: Yuichiro Ishii, Hidehiro Fujiwara, Shinji Tanaka, Yasumasa Tsukamoto, Koji Nii, Yuji Kihara, Kazumasa Yanagisawa

A Low Phase Noise Quadrature Injection Locked Frequency Synthesizer for MM-Wave Applications

Authors: Ahmed Musa, Rui Murakami, Takahiro Sato, Win Chaivipas, Kenichi Okada, Akira Matsuzawa

A Digitized Replica Bitline Delay Technique for Random-Variation-Tolerant Timing Generation of SRAM Sense Amplifiers

Authors: Yusuke Niki, Atsushi Kawasumi, Azuma Suzuki, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Fumihiko Tachibana, Yuki Fujimura, Tomoaki Yabe

A Distributed Oscillator Based All-Digital PLL With a 32-Phase Embedded Phase-to-Digital Converter

Authors: Koji Takinami, Richard Strandberg, Paul C. P. Liang, Gregore Le Grand de Mercey, Tony Wong, Mahnaz Hassibi

Low-OSR Over-Ranging Hybrid ADC Incorporating Noise-Shaped Two-Step Quantizer

Authors: Omid Rajaee, Seiji Takeuchi, Mitsuru Aniya, Koichi Hamashita, Un-Ku Moon

Digitally Assisted IIP2 Calibration for CMOS Direct-Conversion Receivers

Authors: Yiping Feng, Gaku Takemura, Shunji Kawaguchi, Nobuyuki Itoh, Peter R. Kinget

Ultrahigh-Speed Low-Power DACs Using InP HBTs for Beyond-100-Gb/s/ch Optical Transmission Systems

Authors: Munehiko Nagatani, Hideyuki Nosaka, Shogo Yamanaka, Kimikazu Sano, Koichi Murata

A Scalable Massively Parallel Processor for Real-Time Image Processing

Authors: Takashi Kurafuji, Masaru Haraguchi, Masami Nakajima, Tetsu Nishijima, Tetsushi Tanizaki, Hiroyuki Yamasaki, Takeaki Sugimura, Yuta Imai, Masakatsu Ishizaki, Takeshi Kumaki, Kan Murata, Kanako Yoshida, Eisuke Shimomura, Hideyuki Noda, Yoshihiro Okuno, Shunsuke Kamijo, Tetsushi Koide, Hans Jrgen Mattausch, Kazutami Arimoto

Capacitively Coupled Non-Contact Probing Circuits for Membrane-Based Wafer-Level Simultaneous Testing

Authors: Mutsuo Daito, Yoshiro Nakata, Satoshi Sasaki, Hiroyuki Gomyo, Hideki Kusamitsu, Yoshio Komoto, Kunihiko Iizuka, Katsuyuki Ikeuchi, Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai

A Scalable Shield-Bitline-Overdrive Technique for Sub-1.5 V Chain FeRAMs

Authors: Daisaburo Takashima, Hidehiro Shiga, Daisuke Hashimoto, Tadashi Miyakawa, Shinichiro Shiratake, Katsuhiko Hoya, Ryu Ogiwara, Ryosuke Takizawa, Ryosuke Doumae, Ryo Fukuda, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Susumu Shuto, Koji Yamakawa, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama

Generation of Accurate Reference Current for Data Sensing in High-Density Memories by Averaging Multiple Pairs of Dummy Cells

Authors: Takashi Ohsawa, Kosuke Hatsuda, Katsuyuki Fujita, Fumiyoshi Matsuoka, Tomoki Higashi

A 40 nm CMOS 0.4-6 GHz Receiver Resilient to Out-of-Band Blockers

Authors: Jonathan Borremans, Gunjan Mandal, Vito Giannini, Bjrn Debaillie, Mark Ingels, Tomohiro Sano, Bob Verbruggen, Jan Craninckx

1.8 V Low-Transient-Energy Adaptive Program-Voltage Generator Based on Boost Converter for 3D-Integrated NAND Flash SSD

Authors: Koichi Ishida, Tadashi Yasufuku, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi

A Novel Variable Inductor Using a Bridge Circuit and Its Application to a 5-20 GHz Tunable LC-VCO

Authors: Akira Tanabe, Ken'ichiro Hijioka, Hirokazu Nagase, Yoshihiro Hayashi

An Ultra-Wide Range Bi-Directional Transceiver With Adaptive Power Control Using Background Replica VCO Gain Calibration

Authors: Tsuyoshi Ebuchi, Yoshihide Komatsu, Masatomo Miura, Tomoko Chiba, Toru Iwata, Shiro Dosho, Takefumi Yoshikawa

A 0.55 V 10 fJ/bit Inductive-Coupling Data Link and 0.7 V 135 fJ/Cycle Clock Link With Dual-Coil Transmission Scheme

Authors: Noriyuki Miura, Tsunaaki Shidei, Yuxiang Yuan, Shusuke Kawai, Keita Takatsu, Yuji Kiyota, Yuichi Asano, Tadahiro Kuroda

Multi-Step Word-Line Control Technology in Hierarchical Cell Architecture for Scaled-Down High-Density SRAMs

Authors: Koichi Takeda, Toshio Saito, Shinobu Asayama, Yoshiharu Aimoto, Hiroyuki Kobatake, Shinya Ito, Toshifumi Takahashi, Masahiro Nomura, Kiyoshi Takeuchi, Yoshihiro Hayashi

A Large Sigma V TH /VDD Tolerant Zigzag 8T SRAM With Area-Efficient Decoupled Differential Sensing and Fast Write-Back Scheme

Authors: Jui-Jen Wu, Yen-Hui Chen, Meng-Fan Chang, Po-Wei Chou, Chien-Yuan Chen, Hung-Jen Liao, Ming-Bin Chen, Yuan-Hua Chu, Wen-Chin Wu, Hiroyuki Yamauchi

1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing

Authors: Tomonori Sekiguchi, Kazuo Ono, Akira Kotabe, Yoshimitsu Yanagawa

A 530 Mpixels/s 4096x2160@60fps H.264/AVC High Profile Video Decoder Chip

Authors: Dajiang Zhou, Jinjia Zhou, Xun He, Jiayi Zhu, Ji Kong, Peilin Liu, Satoshi Goto

A 100 MHz Ladder FeRAM Design With Capacitance-Coupled-Bitline (CCB) Cell

Authors: Daisaburo Takashima, Yasushi Nagadomi, Tohru Ozaki

A Low-IF/Zero-IF Reconfigurable Analog Baseband IC With an I/Q Imbalance Cancellation Scheme

Authors: Masaki Kitsunezuka, Takashi Tokairin, Tadashi Maeda, Muneo Fukaishi

A 128 Mb Chain FeRAM and System Design for HDD Application and Enhanced HDD Performance

Authors: Daisaburo Takashima, Yasushi Nagadomi, Kosuke Hatsuda, Yohji Watanabe, Shuso Fujii

A 40 nm 222 mW H.264 Full-HD Decoding, 25 Power Domains, 14-Core Application Processor With x512b Stacked DRAM

Authors: Yu Kikuchi, Makoto Takahashi, Tomohisa Maeda, Masatoshi Fukuda, Yasuhiro Koshio, Hiroyuki Hara, Hideho Arakida, Hideaki Yamamoto, Yousuke Hagiwara, Tetsuya Fujita, Manabu Watanabe, Hirokazu Ezawa, Takayoshi Shimazawa, Yasuo Ohara, Takashi Miyamori, Mototsugu Hamada, Masafumi Takahashi, Yukihito Oowaki

A 45 nm SOI Embedded DRAM Macro for the POWER™ Processor 32 MByte On-Chip L3 Cache

Authors: John Barth, Don Plass, Erik Nelson, Charlie Hwang, Gregory Fredeman, Michael A. Sperling, Abraham Mathews, Toshiaki Kirihata, William R. Reohr, Kavita Nair, Nianzheng Caon

User Customizable Logic Paper (UCLP) With Sea-Of Transmission-Gates (SOTG) of 2-V Organic CMOS and Ink-Jet Printed Interconnects

Authors: Koichi Ishida, Naoki Masunaga, Ryo Takahashi, Tsuyoshi Sekitani, Shigeki Shino, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai

A 5 mm2 40 nm LP CMOS Transceiver for a Software-Defined Radio Platform

Authors: Mark Ingels, Vito Giannini, Jonathan Borremans, Gunjan Mandal, Bjrn Debaillie, Peter Van Wesemael, Tomohiro Sano, Takaya Yamamoto, Dries Hauspie, Joris Van Driessche, Jan Craninckx

A 2.1-to-2.8-GHz Low-Phase-Noise All-Digital Frequency Synthesizer With a Time-Windowed Time-to-Digital Converter

Authors: Takashi Tokairin, Mitsuji Okada, Masaki Kitsunezuka, Tadashi Maeda, Muneo Fukaishi

A 10-MHz Signal Bandwidth Cartesian Loop Transmitter Capable of Off-Chip PA Linearization

Authors: Hiroaki Ishihara, Masahiro Hosoya, Shoji Otaka, Osamu Watanabe

A Fully Integrated 2 ˟ 1 Dual-Band Direct-Conversion Mobile WiMAX Transceiver With Dual-Mode Fractional Divider and Noise-Shaping Transimpedance Amplifier in 65 nm CMOS

Authors: Jun Deguchi, Daisuke Miyashita, Yosuke Ogasawara, Gaku Takemura, Masaomi Iwanaga, Kenichi Sami, Rui Ito, Junji Wadatsumi, Yuki Tsuda, Shoko Oda, Shunji Kawaguchi, Nobuyuki Itoh, Mototsugu Hamada

A 12.3-mW 12.5-Gb/s Complete Transceiver in 65-nm CMOS Process

Authors: Koji Fukuda, Hiroki Yamashita, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Noboru Masuda, Takashi Takemoto, Fumio Yuki, Tatsuya Saito

A Millimeter-Wave Intra-Connect Solution

Authors: Kenichi Kawasaki, Yoshiyuki Akiyama, Kenji Komori, Masahiro Uno, Hidenori Takeuchi, Tomoari Itagaki, Yasufumi Hino, Yoshinobu Kawasaki, Katsuhisa Ito, Ali Hajimiri

0.5-V Low- V T CMOS Preamplifier for Low-Power and High-Speed Gigabit-DRAM Arrays

Authors: Akira Kotabe, Yoshimitsu Yanagawa, Satoru Akiyama, Tomonori Sekiguchi

A Low-Supply-Voltage-Operation SRAM With HCI Trimmed Sense Amplifiers

Authors: Atsushi Kawasumi, Yasuhisa Takeyama, Osamu Hirabayashi, Keiichi Kushida, Yuki Fujimura, Tomoaki Yabe

A Low-Power Wide-Range Clock Synchronizer With Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS

Authors: Masafumi Onouchi, Yusuke Kanno, Makoto Saen, Shigenobu Komatsu, Yoshihiko Yasu, Koichiro Ishibashi

An Inductive-Coupling DC Voltage Transceiver for Highly Parallel Wafer-Level Testing

Authors: Yoichi Yoshida, Koichi Nose, Yoshihiro Nakagawa, Koichiro Noguchi, Yasuhiro Morita, Masamoto Tago, Masayuki Mizuno, Tadahiro Kuroda

A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS

Authors: Nikola Nedovic, Anders Kristensson, Samir Parikh, Subodh M. Reddy, Scott McLeod, Nestoras Tzartzanis, Kouichi Kanda, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Takayuki Shibasaki, Yasumoto Tomita, Takayuki Hamada, Mariko Sugawara, Tadashi Ikeuchi, Naoki Kuwata, Hirotaka Tamura, Junji Ogawa, William W. Walker

A 0.13 m SiGe BiCMOS Technology Featuring fT/fmax of 240/330 GHz and Gate Delays Below 3 ps

Authors: Holger Rcker, Bernd Heinemann, Wolfgang Winkler, Rainer Barth, Johannes Borngrber, Jrgen Drews, Gerhard G. Fischer, Alexander Fox, Thomas Grabolla, Ulrich Haak, Dieter Knoll, Falk Korndrfer, Andreas Mai, Steffen Marschmeyer, Peter Schley, Detlef Schmidt, J. Schmidt, Markus Andreas Schubert, K. Schulz, Bernd Tillack, Dirk Wolansky, Yuji Yamamoto

A 60 GHz Power Amplifier With 14.5 dBm Saturation Power and 25% Peak PAE in CMOS 65 nm SOI

Authors: Alexandre Siligaris, Yasuhiro Hamada, Christopher Mounet, Christine Raynaud, Baudouin Martineau, Nicolas Deparis, Nathalie Rolland, Muneo Fukaishi, Pierre Vincent

A Differential Data-Aware Power-Supplied (D 2 AP) 8T SRAM Cell With Expanded Write/Read Stabilities for Lower VDDmin Applications

Authors: Meng-Fan Chang, Jui-Jen Wu, Kuang-Ting Chen, Yung-Chi Chen, Yen-Hui Chen, Robin Lee, Hung-Jen Liao, Hiroyuki Yamauchi

A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb/s Serial Links Over KR-Backplane and Multimode Fiber

Authors: Jun Cao, Bo Zhang, Ullas Singh, Delong Cui, Anand Vasani, Adesh Garg, Wei Zhang, Namik Kocaman, Deyi Pi, Bharath Raghavan, Hui Pan, Ichiro Fujimori, Afshin Momtaz

A 5-Gb/s ADC-Based Feed-Forward CDR in 65 nm CMOS

Authors: Oleksiy Tyshchenko, Ali Sheikholeslami, Hirotaka Tamura, Masaya Kibune, Hisakatsu Yamaguchi, Junji Ogawa

An On-Chip CMOS Relaxation Oscillator With Voltage Averaging Feedback

Authors: Yusuke Tokunaga, Shiro Sakiyama, Akinori Matsumoto, Shiro Dosho

Capacitive-Sensing Circuit Technique for Image Quality Improvement on Fingerprint Sensor LSIs

Authors: Toshishige Shimamura, Hiroki Morimura, Satoshi Shigematsu, Mamoru Nakanishi, Katsuyuki Machida

A Fifth-Order Continuous-Time Delta-Sigma Modulator With Single-Opamp Resonator

Authors: Kazuo Matsukawa, Yosuke Mitani, Masao Takayama, Koji Obata, Shiro Dosho, Akira Matsuzawa

3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link

Authors: Makoto Saen, Kenichi Osada, Yasuyuki Okuma, Kiichi Niitsu, Yasuhisa Shimazaki, Yasufumi Sugimori, Yoshinori Kohama, Kazutaka Kasuga, Itaru Nonomura, Naohiko Irie, Toshihiro Hattori, Atsushi Hasegawa, Tadahiro Kuroda

A 77 GHz 90 nm CMOS Transceiver for FMCW Radar Applications

Authors: Toshiya Mitomo, Naoko Ono, Hiroaki Hoshino, Yoshiaki Yoshihara, Osamu Watanabe, Ichiro Seto

Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma/Pipelined ADC

Authors: Omid Rajaee, Tawfiq Musah, Nima Maghari, Seiji Takeuchi, Mitsuru Aniya, Koichi Hamashita, Un-Ku Moon

A Background Self-Calibrated 6b 2.7 GS/s ADC With Cascade-Calibrated Folding-Interpolating Architecture

Authors: Yuji Nakajima, Akemi Sakaguchi, Toshio Ohkido, Norihito Kato, Tetsuya Matsumoto, Michio Yotsuyanagi

A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and '1'/'0' Dual-Array Equalized Reference Scheme

Authors: Riichiro Takemura, Takayuki Kawahara, Katsuya Miura, Hiroyuki Yamamoto, Jun Hayakawa, Nozomu Matsuzaki, Kazuo Ono, Michihiko Yamanouchi, Kenchi Ito, Hiromasa Takahashi, Shoji Ikeda, Haruhiro Hasegawa, Hideyuki Matsuoka, Hideo Ohno

LMS-Based Noise Leakage Calibration of Cascaded Continuous-Time Delta Sigma Modulators

Authors: Yun-Shiang Shu, Junpei Kamiishi, Koji Tomioka, Koichi Hamashita, Bang-Sup Song

A Chip-Stacked Memory for On-Chip SRAM-Rich SoCs and Processors

Authors: Hideaki Saito, Masayuki Nakajima, Takumi Okamoto, Yusuke Yamada, Akira Ohuchi, Noriyuki Iguchi, Toshitsugu Sakamoto, Koichi Yamaguchi, Masayuki Mizuno

Stretchable EMI Measurement Sheet With 8 ˟ 8 Coil Array, 2 V Organic CMOS Decoder, and 0.18 μ m Silicon CMOS LSIs for Electric and Magnetic Field Detection

Authors: Koichi Ishida, Naoki Masunaga, Zhiwei Zhou, Tadashi Yasufuku, Tsuyoshi Sekitani, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai

A 1.6 GB/s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes

Authors: Hidehiro Shiga, Daisaburo Takashima, Shinichiro Shiratake, Katsuhiko Hoya, Tadashi Miyakawa, Ryu Ogiwara, Ryo Fukuda, Ryosuke Takizawa, Kosuke Hatsuda, Fumiyoshi Matsuoka, Yasushi Nagadomi, Daisuke Hashimoto, Hisaaki Nishimura, Takeshi Hioka, Sumiko Doumae, Shoichi Shimizu, Mitsumo Kawano, Toyoki Taguchi, Yohji Watanabe, Shuso Fujii, Tohru Ozaki, Hiroyuki Kanaya, Yoshinori Kumura, Yoshiro Shimojo, Yuki Yamada, Yoshihiro Minami, Susumu Shuto, Koji Yamakawa, Soichi Yamazaki, Iwao Kunishima, Takeshi Hamamoto, Akihiro Nitayama, Tohru Furuyama

2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking

Authors: Mitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda

A 342 mW Mobile Application Processor With Full-HD Multi-Standard Video Codec and Tile-Based Address-Translation Circuits

Authors: Kenichi Iwata, Takahiro Irita, Seiji Mochizuki, Hiroshi Ueda, Masakazu Ehama, Motoki Kimura, Jun Takemura, Keiji Matsumoto, Eiji Yamamoto, Tadashi Teranuma, Katsuji Takakubo, Hiromi Watanabe, Shinichi Yoshioka, Toshihiro Hattori

A 40 Gb/s Multi-Data-Rate CMOS Transmitter and Receiver Chipset With SFI-5 Interface for Optical Transmission Systems

Authors: Shunichi Kaeriyama, Yasushi Amamiya, Hidemi Noguchi, Zin Yamazaki, Tomoyuki Yamase, Ken'ichi Hosoya, Minoru Okamoto, Shiro Tomari, Hiroshi Yamaguchi, Hiroaki Shoda, Hironobu Ikeda, Shinji Tanaka, Tsugio Takahashi, Risato Ohhira, Arihide Noda, Ken'ichiro Hijioka, Akira Tanabe, Sadao Fujita, Nobuhiro Kawahara

A Charge-Multiplication CMOS Image Sensor Suitable for Low-Light-Level Imaging

Authors: Ryu Shimizu, Mamoru Arimoto, Hayato Nakashima, Kaori Misawa, Toshikazu Ohno, Yugo Nose, Keisuke Watanabe, Tatsushi Ohyama

A 4-Channel 1.25-10.3 Gb/s Backplane Transceiver Macro With 35 dB Equalizer and Sign-Based Zero-Forcing Adaptive Control

Authors: Yasuo Hidaka, Weixin Gai, Takeshi Horie, Jian Hong Jiang, Yoichi Koyanagi, Hideki Osone

A 10-Gb/s Receiver With Track-and-Hold-Type Linear Phase Detector and Charge-Redistribution First-Order ΔΣ Modulator in 90-nm CMOS

Authors: Koji Fukuda, Hiroki Yamashita, Fumio Yuki, Goichi Ono, Ryo Nemoto, Eiichi Suzuki, Takashi Takemoto, Masashi Kono, Tatsuya Saito

A 2.0 Gb/s Clock-Embedded Interface for Full-HD 10-Bit 120 Hz LCD Drivers With 1/5-Rate Noise-Tolerant Phase and Frequency Recovery

Authors: Koichi Yamaguchi, Yoshihiko Hori, Keiichi Nakajima, Kazumasa Suzuki, Masayuki Mizuno, Hiroshi Hayama

An Embedded 65 nm CMOS Baseband IQ 48 MHz-1 GHz Dual Tuner for DOCSIS 3.0

Authors: Francesco Gatta, Ray Gomez, Young J. Shin, Takayuki Hayashi, Hanli Zou, James Y. C. Chang, Leonard Dauphinee, Jianhong Xiao, Dave S.-H. Chang, Tai-Hong Chih, Massimo Brandolini, Dongsoo Koh, Bryan Juo-Jung Hung, Tao Wu, Mattia Introini, Giuseppe Cusmai, Ertan Zencir, Frank Singor, Hans Eberhart, Loke Kun Tan, Bruce Currivan, Lin He, Peter Cangiane, Pieter Vorenkamp

A Single-40 Gb/s Dual-20 Gb/s Serializer IC With SFI-5.2 Interface in 65 nm CMOS

Authors: Kouichi Kanda, Hirotaka Tamura, Takuji Yamamoto, Satoshi Matsubara, Masaya Kibune, Yoshiyasu Doi, Takayuki Shibasaki, Nestoras Tzartzanis, Anders Kristensson, Samir Parikh, Satoshi Ide, Yukito Tsunoda, Tetsuji Yamabana, Mariko Sugawara, Naoki Kuwata, Tadashi Ikeuchi, Junji Ogawa, William W. Walker

Design of a 770-MHz, 70-mW, 8-bit Subranging ADC Using Reference Voltage Precharging Architecture

Authors: Kenichi Ohhata, Koki Uchino, Yuichiro Shimizu, Kosuke Oyama, Kiichi Yamashita

High-Efficiency Differential-Drive CMOS Rectifier for UHF RFIDs

Authors: Koji Kotani, Atsushi Sasaki, Takashi Ito

ROM-Based Logic (RBL) Design: A Low-Power 16 Bit Multiplier

Authors: Bipul C. Paul, Shinobu Fujita, Masaki Okajima

A Power, Performance Scalable Eight-Cores Media Processor for Mobile Multimedia Applications

Authors: Tatsuya Mori, Yasuyuki Ueda, Nobuhiro Nonogaki, Toshihiro Terazawa, Milosz Sroka, Tetsuya Fujita, Takeshi Kodaka, Takayuki Mori, Kumiko Morita, Hideho Arakida, Takashi Miura, Yuji Okuda, Toshiki Kizu, Yoshiro Tsuboi

Accurate Array-Based Measurement for Subthreshold-Current of MOS Transistors

Authors: Takashi Sato, Hiroyuki Ueyama, Noriaki Nakayama, Kazuya Masu

A 0.6-V Dynamic Biasing Filter With 89-dB Dynamic Range in 0.18-m CMOS

Authors: Ippei Akita, Kazuyuki Wada, Yoshiaki Tadokoro

Intermittent Operation Control Scheme for Reducing Power Consumption of UWB-IR Receiver

Authors: Takahide Terada, Ryosuke Fujiwara, Goichi Ono, Takayasu Norimatsu, Tatsuo Nakagawa, Masayuki Miyazaki, Kei Suzuki, Kazuo Yano, Akira Maeki, Yuji Ogata, Shinsuke Kobayashi, Noboru Koshizuka, Ken Sakamura

A Low Power Pipelined ADC Using Capacitor and Opamp Sharing Technique With a Scheme to Cancel the Effect of Signal Dependent Kickback

Authors: Naga Sasidhar, Youn-Jae Kook, Seiji Takeuchi, Koichi Hamashita, Kaoru Takasuka, Pavan Kumar Hanumolu, Un-Ku Moon

A Fifth-Order Gm-C Continuous-Time ΔΣ Modulator With Process-Insensitive Input Linear Range

Authors: Yusuke Aiba, Koji Tomioka, Yuta Nakashima, Koichi Hamashita, Bang-Sup Song

A Widely-Tunable, Reconfigurable CMOS Analog Baseband IC for Software-Defined Radio

Authors: Masaki Kitsunezuka, Shinichi Hori, Tadashi Maeda

Nonvolatile Magnetic Flip-Flop for Standby-Power-Free SoCs

Authors: Noboru Sakimura, Tadahiko Sugibayashi, Ryusuke Nebashi, Naoki Kasai

A Zero-IF 60 GHz 65 nm CMOS Transceiver With Direct BPSK Modulation Demonstrating up to 6 Gb/s Data Rates Over a 2 m Wireless Link

Authors: Alexander Tomkins, Ricardo Andres Aroca, Takuji Yamamoto, Sean T. Nicolson, Yoshiyasu Doi, Sorin P. Voinigescu

Heterogeneous Multicore SoC With SiP for Secure Multimedia Applications

Authors: Hiroyuki Kondo, Sugako Otani, Masami Nakajima, Osamu Yamamoto, Norio Masui, Naoto Okumura, Mamoru Sakugawa, Masaya Kitao, Koichi Ishimi, Masayuki Sato, Fumitaka Fukuzawa, Satoshi Imasu, Nobuhiro Kinoshita, Yusuke Ota, Kazutami Arimoto, Toru Shimizu

A 300 nW, 15 ppm°C, 20 ppm/V CMOS Voltage Reference Circuit Consisting of Subthreshold MOSFETs

Authors: Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya

A 100 MS/s 4 MHz Bandwidth 70 dB SNR ΔΣ ADC in 90 nm CMOS

Authors: Yoshihisa Fujimoto, Yusuke Kanazawa, Pascal Lo R, Kunihiko Iizuka

All-Digital Ring-Oscillator-Based Macro for Sensing Dynamic Supply Noise Waveform

Authors: Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye

A 1 MB Cache Subsystem Prototype With 1.8 ns Embedded DRAMs in 45 nm SOI CMOS

Authors: Peter J. Klim, John Barth, William R. Reohr, David Dick, Gregory Fredeman, Gary Koch, Hien M. Le, Aditya Khargonekar, Pamela Wilcox, John Golz, Jente B. Kuang, Abraham Mathews, Jethro C. Law, Trong Luong, Hung C. Ngo, Ryan Freese, Hillery C. Hunter, Erik Nelson, Paul C. Parries, Toshiaki Kirihata, Subramanian S. Iyer

A 0.6 V Dual-Rail Compiler SRAM Design on 45 nm CMOS Technology With Adaptive SRAM Power for Lower VDD_min VLSIs

Authors: Yen-Huei Chen, Gary Chan, Shao-Yu Chou, Hsien-Yu Pan, Jui-Jen Wu, Robin Lee, Hung-Jen Liao, Hiroyuki Yamauchi

A 256 mW 40 Mbps Full-HD H.264 High-Profile Codec Featuring a Dual-Macroblock Pipeline Architecture in 65 nm CMOS

Authors: Kenichi Iwata, Seiji Mochizuki, Motoki Kimura, Tetsuya Shibayama, Fumitaka Izuhara, Hiroshi Ueda, Koji Hosogi, Hiroaki Nakata, Masakazu Ehama, Toru Kengaku, Takuichiro Nakazawa, Hiromi Watanabe

A Sub-s Wake-Up Time Power Gating Technique With Bypass Power Line for Rush Current Support

Authors: Kenichi Kawasaki, Tetsuyoshi Shiota, Koichi Nakayama, Atsuki Inoue

A 0.7 V Single-Supply SRAM With 0.495 m2 Cell in 65 nm Technology Utilizing Self-Write-Back Sense Amplifier and Cascaded Bit Line Scheme

Authors: Keiichi Kushida, Azuma Suzuki, Gou Fukano, Atsushi Kawasumi, Osamu Hirabayashi, Yasuhisa Takeyama, Takahiko Sasaki, Akira Katayama, Yuki Fujimura, Tomoaki Yabe

A 0.8 V, 2.6 mW, 88 dB Dual-Channel Audio Delta-Sigma D/A Converter With Headphone Driver

Authors: Kyehyung Lee, Qingdong Meng, Tetsuro Sugimoto, Koichi Hamashita, Kaoru Takasuka, Seiji Takeuchi, Un-Ku Moon, Gabor C. Temes

A 125-1250 MHz Process-Independent Adaptive Bandwidth Spread Spectrum Clock Generator With Digital Controlled Self-Calibration

Authors: Tsuyoshi Ebuchi, Yoshihide Komatsu, Tatsuo Okamoto, Yukio Arima, Yuji Yamada, Kazuaki Sogawa, Kouji Okamoto, Takashi Morie, Takashi Hirata, Shiro Dosho, Takefumi Yoshikawa

A High-Speed Inductive-Coupling Link With Burst Transmission

Authors: Noriyuki Miura, Yoshinori Kohama, Yasufumi Sugimori, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda

Synchronous Ultra-High-Density 2RW Dual-Port 8T-SRAM With Circumvention of Simultaneous Common-Row-Access

Authors: Koji Nii, Yasumasa Tsukamoto, Makoto Yabuuchi, Yasuhiro Masuda, Susumu Imaoka, Keiichi Usui, Shigeki Ohbayashi, Hiroshi Makino, Hirofumi Shinohara

HDTV1080p H.264/AVC Encoder Chip Design and Performance Analysis

Authors: Zhenyu Liu, Yang Song, Ming Shao, Shen Li, Lingfeng Li, Shunichi Ishiwata, Masaki Nakagawa, Satoshi Goto, Takeshi Ikenaga

A 750 Mb/s, 12 pJ/b, 6-to-10 GHz CMOS IR-UWB Transmitter With Embedded On-Chip Antenna

Authors: Vishal V. Kulkarni, Muhammad Muqsith, Kiichi Niitsu, Hiroki Ishikuro, Tadahiro Kuroda

A 65 nm Single-Chip Application and Dual-Mode Baseband Processor With Partial Clock Activation and IP-MMU

Authors: Masayuki Ito, Kenichi Nitta, Koji Ohno, Masahito Saigusa, Masaki Nishida, Shinichi Yoshioka, Takahiro Irita, Takao Koike, Tatsuya Kamei, Teruyoshi Komuro, Toshihiro Hattori, Yasuhiro Arai, Yukio Kodama

Architecture and Physical Implementation of a Third Generation 65 nm, 16 Core, 32 Thread Chip-Multithreading SPARC Processor

Authors: Georgios K. Konstadinidis, Marc Tremblay, Shailender Chaudhry, Mamun Rashid, Peter F. Lai, Yukio Otaguro, Yannis Orginos, Sudhendra Parampalli, Mark Steigerwald, Shriram Gundala, Rambabu Pyapali, Leonard Rarick, Ilyas Elkin, Yuefei Ge, Ishwar Parulkar

A 34 MB/s MLC Write Throughput 16 Gb NAND With All Bit Line Architecture on 56 nm Technology

Authors: Raul Cernea, Long Pham, Farookh Moogat, Siu Lung Chan, Binh Le, Yan Li, Shouchang Tsao, Taiyuan Tseng, Khanh Nguyen, Jason Li, Jayson Hu, Jonghak Yuh, Cynthia Hsu, Fanglin Zhang, Teruhiko Kamei, Hiroaki Nasu, Phil Kliza, Khin Htoo, Jeffrey Lutze, Yingda Dong, Masaaki Higashitani, Junhui Yang, Hung-Szu Lin, Vamshi Sakhamuri, Alan Li, Feng Pan, Sridhar Yadala, Subodh Taigor, Kishan Pradhan, James Lan, Jim Chan, Takumi Abe, Yasuyuki Fukuda, Hideo Mukai, Koichi Kawakami, Connie Liang, Tommy Ip, Shu-Fen Chang, Jaggi Lakshmipathi, Sharon Huynh, Dimitris Pantelakis, Mehrdad Mofidi, Khandker Quader

A 16 Gb 3-Bit Per Cell (X3) NAND Flash Memory on 56 nm Technology With 8 MB/s Write Rate

Authors: Yan Li, Seungpil Lee, Yupin Fong, Feng Pan, Tien-Chien Kuo, Jongmin Park, Tapan Samaddar, Hao Nguyen, Man Mui, Khin Htoo, Teruhiko Kamei, Masaaki Higashitani, Emilio Yero, Gyuwan Kwon, Phil Kliza, Jun Wan, Tetsuya Kaneko, Hiroshi Maejima, Hitoshi Shiga, Makoto Hamada, Norihiro Fujita, Kazunori Kanebako, Eugene Tam, Anne Koh, Iris Lu, Calvin Chia-Hong Kuo, Trung Pham, Jonathan Huynh, Qui Nguyen, Hardwell Chibvongodze, Mitsuyuki Watanabe, Ken Oowada, Grishma Shah, Byungki Woo, Ray Gao, Jim Chan, James Lan, Patrick Hong, Liping Peng, Debi Das, Dhritiman Ghosh, Vivek Kalluru, Sanjay Kulkarni, Raul-Adrian Cernea, Sharon Huynh, Dimitris Pantelakis, Chi-Ming Wang, Khandker Quader

Introduction to the Special Issue on the 2008 IEEE International Solid-State Circuits Conference

Authors: Sanroku Tsukamoto, Shen-Iuan Liu, Stefan Heinen, Roland Thewes, Jri Lee

A 40-Gb/s CDR Circuit With Adaptive Decision-Point Control Based on Eye-Opening Monitor Feedback

Authors: Hidemi Noguchi, Nobuhide Yoshida, Hiroaki Uchida, Manabu Ozaki, Shunichi Kanemitsu, Shigeki Wada

A Noise-Coupled Time-Interleaved Delta-Sigma ADC With 4.2 MHz Bandwidth, -98 dB THD, and 79 dB SNDR

Authors: Kyehyung Lee, Jeongseok Chae, Mitsuru Aniya, Koichi Hamashita, Kaoru Takasuka, Seiji Takeuchi, Gabor C. Temes

A Fully-Integrated Quad-Band GSM/GPRS CMOS Power Amplifier

Authors: Ichiro Aoki, Scott Kee, Rahul Magoon, Roberto Aparicio, Florian Bohn, Jeff Zachan, Geoff Hatcher, Donald McClymont, Ali Hajimiri

A 10.3 Gb/s Burst-Mode CDR Using a ΔΣ DAC

Authors: Jun Terada, Kazuyoshi Nishimura, Shunji Kimura, Hiroaki Katsurai, Naoto Yoshimoto, Yusuke Ohtomo

Backgate Bias Accelerator for sub-100 ns Sleep-to-Active Modes Transition Time

Authors: David Levacq, Makoto Takamiya, Takayasu Sakurai

A 64 mW High Picture Quality H.264/MPEG-4 Video Codec IP for HD Mobile Applications in 90 nm CMOS

Authors: Seiji Mochizuki, Tetsuya Shibayama, Masaru Hase, Fumitaka Izuhara, Kazushi Akie, Masaki Nobori, Ren Imaoka, Hiroshi Ueda, Kazuyuki Ishikawa, Hiromi Watanabe

A 6-bit 3.5-GS/s 0.9-V 98-mW Flash ADC in 90-nm CMOS

Authors: Kazuaki Deguchi, Naoko Suwa, Masao Ito, Toshio Kumamoto, Takahiro Miki

A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses

Authors: Toshikazu Suzuki, Hiroyuki Yamauchi, Yoshinobu Yamagami, Katsuji Satomi, Hironori Akamatsu

A Delta-Sigma Modulator With a Widely Programmable Center Frequency and 82-dB Peak SNDR

Authors: Kentaro Yamamoto, Anthony Chan Carusone, Francis P. Dawson

An Assessment of -Czochralski, Single-Grain Silicon Thin-Film Transistor Technology for Large-Area, Sensor and 3-D Electronic Integration

Authors: Nitz Saputra, Mina Danesh, Alessandro Baiano, Ryoichi Ishihara, John R. Long, Nobuo Karaki, Satoshi Inoue

An 8T-SRAM for Variability Tolerance and Low-Voltage Operation in High-Performance Caches

Authors: Leland Chang, Robert K. Montoye, Yutaka Nakamura, Kevin Batson, Richard J. Eickemeyer, Robert H. Dennard, Wilfried Haensch, Damir Jamsek

A Bidirectional- and Multi-Drop-Transmission-Line Interconnect for Multipoint-to-Multipoint On-Chip Communications

Authors: Hiroyuki Ito, Makoto Kimura, Kazuya Miyashita, Takahiro Ishii, Kenichi Okada, Kazuya Masu

Memory at VLSI Circuits Symposium

Authors: Kiyoo Itoh, Hideaki Kurata, Kenichi Osada, Tomonori Sekiguchi

A 200-V/e- CMOS Image Sensor With 100-ke- Full Well Capacity

Authors: Satoru Adachi, Woonghee Lee, Nana Akahane, Hiromichi Oshikubo, Koichi Mizobuchi, Shigetoshi Sugawa

A Design Method and Developments of a Low-Power and High-Resolution Multiphase Generation System

Authors: Akinori Matsumoto, Shiro Sakiyama, Yusuke Tokunaga, Takashi Morie, Shiro Dosho

Design and Implementation of a Configurable Heterogeneous Multicore SoC With Nine CPUs and Two Matrix Processors

Authors: Hiroyuki Kondo, Masami Nakajima, Norio Masui, Sugako Otani, Naoto Okumura, Yukari Takata, Takashi Nasu, Hirokazu Takata, Takashi Higuchi, Mamoru Sakugawa, Hayato Fujiwara, Kazuya Ishida, Koichi Ishimi, Satoshi Kaneko, Teruyuki Itoh, Masayuki Sato, Osamu Yamamoto, Kazutami Arimoto

A 60-GHz CMOS Receiver Front-End With Frequency Synthesizer

Authors: Toshiya Mitomo, Ryuichi Fujimoto, Naoko Ono, Ryoichi Tachibana, Hiroaki Hoshino, Yoshiaki Yoshihara, Yukako Tsutsumi, Ichiro Seto

1-cc Computer: Cross-Layer Integration With UWB-IR Communication and Locationing

Authors: Tatsuo Nakagawa, Goichi Ono, Ryosuke Fujiwara, Takayasu Norimatsu, Takahide Terada, Masayuki Miyazaki, Kei Suzuki, Kazuo Yano, Yuji Ogata, Akira Maeki, Shinsuke Kobayashi, Noboru Koshizuka, Ken Sakamura

A 70 nm 16 Gb 16-Level-Cell NAND flash Memory

Authors: Noboru Shibata, Hiroshi Maejima, Katsuaki Isobe, Kiyoaki Iwasa, Michio Nakagawa, Masaki Fujiu, Takahiro Shimizu, Mitsuaki Honma, Satoru Hoshi, Toshimasa Kawaai, Kazunori Kanebako, Susumu Yoshikawa, Hideyuki Tabata, Atsushi Inoue, Toshiyuki Takahashi, Toshifumi Shano, Yukio Komatsu, Katsushi Nagaba, Mitsuhiko Kosakai, Noriaki Motohashi, Kazuhisa Kanazawa, Kenichi Imamiya, Hiroto Nakai, Menahem Lasser, Mark Murin, Avraham Meir, Arik Eyal, Mark Shlick

A 45 nm 2-port 8T-SRAM Using Hierarchical Replica Bitline Technique With Immunity From Simultaneous R/W Access Issues

Authors: Satoshi Ishikura, Marefusa Kurumada, Toshio Terano, Yoshinobu Yamagami, Naoki Kotani, Katsuji Satomi, Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Toshiyuki Oashi, Hiroshi Makino, Hirofumi Shinohara, Hironori Akamatsu

Heterogeneous Multi-Core Architecture That Enables 54x AAC-LC Stereo Encoding

Authors: Hiroaki Shikano, Masaki Ito, Masafumi Onouchi, Takashi Todaka, Takanobu Tsunoda, Tomoyuki Kodama, Kunio Uchiyama, Toshihiko Odaka, Tatsuya Kamei, Ei Nagahama, Manabu Kusaoke, Yusuke Nitta, Yasutaka Wada, Keiji Kimura, Hironori Kasahara

A Circuit for Determining the Optimal Supply Voltage to Minimize Energy Consumption in LSI Circuit Operations

Authors: Yoshifumi Ikenaga, Masahiro Nomura, Yoetsu Nakazawa, Yasuhiko Hagihara

20-GHz Quadrature Injection-Locked LC Dividers With Enhanced Locking Range

Authors: Takayuki Shibasaki, Hirotaka Tamura, Kouichi Kanda, Hisakatsu Yamaguchi, Junji Ogawa, Tadahiro Kuroda

Measurement and Analysis of Inductive Coupling Noise in 90 nm Global Interconnects

Authors: Yasuhiro Ogasahara, Masanori Hashimoto, Takao Onoye

ΔΣ PLL Transmitter With a Loop-Bandwidth Calibration System

Authors: Yukinori Akamine, Manabu Kawabe, Kazuyuki Hori, Takao Okazaki, Masumi Kasahara, Satoshi Tanaka

A Programmable Impedance Matching Circuit for Voiceband Modems

Authors: Russell A. Hershbarger, Wenyan Jia, Kiam M. Tey, Kiyoshi Fukahori, Paul J. Hurst, Manprit Kapoor

Implementation of the Cell Broadband Engine™ in 65 nm SOI Technology Featuring Dual Power Supply SRAM Arrays Supporting 6 GHz at 1.3 V

Authors: Juergen Pille, Chad Adams, Todd Christensen, Scott R. Cottier, Sebastian Ehrenreich, Fumihiro Kono, Daniel Nelson, Osamu Takahashi, Shunsako Tokito, Otto A. Torreiter, Otto Wagner, Dieter F. Wendel

A 45-nm Bulk CMOS Embedded SRAM With Improved Immunity Against Process and Temperature Variations

Authors: Koji Nii, Makoto Yabuuchi, Yasumasa Tsukamoto, Shigeki Ohbayashi, Susumu Imaoka, Hiroshi Makino, Yoshinobu Yamagami, Satoshi Ishikura, Toshio Terano, Toshiyuki Oashi, Keiji Hashimoto, Akio Sebe, Gen Okazaki, Katsuji Satomi, Hironori Akamatsu, Hirofumi Shinohara

2 Mb SPRAM (SPin-Transfer Torque RAM) With Bit-by-Bit Bi-Directional Current Write and Parallelizing-Direction Current Read

Authors: Takayuki Kawahara, Riichiro Takemura, Katsuya Miura, Jun Hayakawa, Shoji Ikeda, Young Min Lee, Ryutaro Sasaki, Yasushi Goto, Kenchi Ito, Toshiyasu Meguro, Fumihiro Matsukura, Hiromasa Takahashi, Hideyuki Matsuoka, Hideo Ohno

UHF RFCPUs on Flexible and Glass Substrates for Secure RFID Systems

Authors: Yoshiyuki Kurokawa, Takayuki Ikeda, Masami Endo, Hiroki Dembo, Daisuke Kawae, Takayuki Inoue, Munehiro Kozuma, Daisuke Ohgarane, Satoru Saito, Koji Dairiki, Hidekazu Takahashi, Yutaka Shionoiri, Tomoaki Atsumi, Takeshi Osada, Kei Takahashi, Takanori Matsuzaki, Hiroyuki Takashina, Yoshinari Yamashita, Shunpei Yamazaki

A 500 MHz Random Cycle, 1.5 ns Latency, SOI Embedded DRAM Macro Featuring a Three-Transistor Micro Sense Amplifier

Authors: John Barth, William R. Reohr, Paul C. Parries, Gregory Fredeman, John Golz, Stanley Schuster, Richard E. Matick, Hillery C. Hunter, Charles Tanner, Joseph Harig, Hoki Kim, Babar Khan, John Griesemer, Robert Havreluk, Kenji Yanagisawa, Toshiaki Kirihata, Subramanian S. Iyer

A 65 nm Embedded SRAM With Wafer Level Burn-In Mode, Leak-Bit Redundancy and Cu E-Trim Fuse for Known Good Die

Authors: Shigeki Ohbayashi, Makoto Yabuuchi, Kazushi Kono, Yuji Oda, Susumu Imaoka, Keiichi Usui, Toshiaki Yonezu, Takeshi Iwamoto, Koji Nii, Yasumasa Tsukamoto, Masashi Arakawa, Takahiro Uchida, Masakazu Okada, Atsushi Ishii, Tsutomu Yoshihara, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara

A 0.14 pJ/b Inductive-Coupling Transceiver With Digitally-Controlled Precise Pulse Shaping

Authors: Noriyuki Miura, Hiroki Ishikuro, Kiichi Niitsu, Takayasu Sakurai, Tadahiro Kuroda

A 40-44 Gb/s 3 Oversampling CMOS CDR/1: 16 DEMUX

Authors: Nikola Nedovic, Nestoras Tzartzanis, Hirotaka Tamura, Francis M. Rotella, Magnus Wiklund, Yuma Mizutani, Yusuke Okaniwa, Tadahiro Kuroda, Junji Ogawa, William W. Walker

A 1/2.7-in 2.96 MPixel CMOS Image Sensor With Double CDS Architecture for Full High-Definition Camcorders

Authors: Hidekazu Takahashi, Tomoyuki Noda, Takashi Matsuda, Takanori Watanabe, Mahito Shinohara, Toshiaki Endo, Shunsuke Takimoto, Ryuichi Mishima, Shigeru Nishimura, Katsuhito Sakurai, Hiroshi Yuzurihara, Shunsuke Inoue

A Continuous-Grain Silicon-System LCD With Optical Input Function

Authors: Chris J. Brown, Hiromi Kato, Kazuhiro Maeda, Ben Hadwen

A 16-Mb Toggle MRAM With Burst Modes

Authors: Tadahiko Sugibayashi, Noboru Sakimura, Takeshi Honda, Kiyokazu Nagahara, Kiyotaka Tsuji, Hideaki Numata, Sadahiko Miura, Ken-ichi Shimura, Yuko Kato, Shinsaku Saito, Yoshiyuki Fukumoto, Hiroaki Honjo, Tetsuhiro Suzuki, Katsumi Suemitsu, Tomonori Mukai, Kaoru Mori, Ryusuke Nebashi, Shunsuke Fukami, Norikazu Ohshima, Hiromitsu Hada, Nobuyuki Ishiwata, Naoki Kasai, Shuichi Tahara

Over-100-Gb/s 1: 2 Demultiplexer Based on InP HBT Technology

Authors: Yasuyuki Suzuki, Masayuki Mamada, Zin Yamazaki

A Digitally Controlled Variable-Gain Low-Noise Amplifier With Strong Immunity to Interferers

Authors: Masato Koutani, Hiroshi Kawamura, Shinji Toyoyama, Kunihiko Iizuka

Stacked-Chip Implementation of On-Chip Buck Converter for Distributed Power Supply System in SiPs

Authors: Kohei Onizuka, Kenichi Inagaki, Hiroshi Kawaguchi, Makoto Takamiya, Takayasu Sakurai

A High-Density Scalable Twin Transistor RAM (TTRAM) With Verify Control for SOI Platform Memory IPs

Authors: Kazutami Arimoto, Fukashi Morishita, Isamu Hayashi, Katsumi Dosaka, Hiroki Shimano, Takashi Ipposhi

A 3.2 Gb/s CDR Using Semi-Blind Oversampling to Achieve High Jitter Tolerance

Authors: Marcus van Ierssel, Ali Sheikholeslami, Hirotaka Tamura, William W. Walker

A High-Power Low-Distortion GaAs HBT Power Amplifier for Mobile Terminals Used in Broadband Wireless Applications

Authors: Tohru Oka, Masatomo Hasegawa, Michitoshi Hirata, Yoshihisa Amano, Yoshiteru Ishimaru, Hiroshi Kawamura, Keiichi Sakuno

22-29 GHz Ultra-Wideband CMOS Pulse Generator for Short-Range Radar Applications

Authors: Ahmet nc, B. B. M. Wasanthamala Badalawa, Minoru Fujishima

A UWB-IR Transmitter With Digitally Controlled Pulse Generator

Authors: Takayasu Norimatsu, Ryosuke Fujiwara, Masaru Kokubo, Masayuki Miyazaki, Akira Maeki, Yuji Ogata, Shinsuke Kobayashi, Noboru Koshizuka, Ken Sakamura

Random Telegraph Signal in Flash Memory: Its Impact on Scaling of Multilevel Flash Memory Beyond the 90-nm Node

Authors: Hideaki Kurata, Kazuo Otsuga, Akira Kotabe, Shinya Kajiyama, Taro Osabe, Yoshitaka Sasago, Shunichi Narumi, Kenji Tokami, Shiro Kamohara, Osamu Tsuchiya

A CDMA InGaP/GaAs-HBT MMIC Power Amplifier Module Operating With a Low Reference Voltage of 2.4 V

Authors: Kazuya Yamamoto, Takao Moriwaki, Hiroyuki Otsuka, Nobuyuki Ogawa, Kosei Maemura, Teruyuki Shimura

Analytical Determination of MOSFET's High-Frequency Noise Parameters From NF50 Measurements and Its Application in RFIC Design

Authors: Saman Asgaran, M. Jamal Deen, Chih-Hung Chen, G. Ali Rezvani, Yasmin Kamali, Yukihiro Kiyota

The Circuits and Robust Design Methodology of the Massively Parallel Processor Based on the Matrix Architecture

Authors: Hideyuki Noda, Tetsushi Tanizaki, Takayuki Gyohten, Katsumi Dosaka, Masami Nakajima, Katsuya Mizumoto, Kanako Yoshida, Takenobu Iwao, Tetsu Nishijima, Yoshihiro Okuno, Kazutami Arimoto

A 184 mW Fully Integrated DVB-H Tuner With a Linearized Variable Gain LNA and Quadrature Mixers Using Cross-Coupled Transconductor

Authors: Kunihiko Iizuka, Hiroshi Kawamura, Takanobu Fujiwara, Kanetomo Kagoshima, Shuichi Kawama, Hiroshi Kijima, Masato Koutani, Shinji Toyoyama, Keiichi Sakuno

CMOS Smart Sensor for Monitoring the Quality of Perishables

Authors: Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya

A 0.79-mm2 29-mW Real-Time Face Detection Core

Authors: Yuichi Hori and Tadahiro Kuroda

A Fully Integrated 10-Gb/s Receiver With Adaptive Optical Dispersion Equalizer in 0.13-m CMOS

Authors: Afshin Momtaz, David Chung, Namik Kocaman, Jun Cao, Mario Caresosa, Bo Zhang, Ichiro Fujimori

A Configurable Enhanced TTRAM Macro for System-Level Power Management Unified Memory

Authors: Fukashi Morishita, Isamu Hayashi, Takayuki Gyohten, Hideyuki Noda, Takashi Ipposhi, Hiroki Shimano, Katsumi Dosaka, Kazutami Arimoto

MRAM Cell Technology for Over 500-MHz SoC

Authors: Noboru Sakimura, Tadahiko Sugibayashi, Takeshi Honda, Hiroaki Honjo, Shinsaku Saito, Tetsuhiro Suzuki, Nobuyuki Ishiwata, Shuichi Tahara

In-Situ Measurement of Supply-Noise Maps With Millivolt Accuracy and Nanosecond-Order Time Resolution

Authors: Yusuke Kanno, Yuki Kondoh, Takahiro Irita, Kenji Hirose, Ryo Mori, Yoshihiko Yasu, Shigenobu Komatsu, Hiroyuki Mizuno

A 65-nm SoC Embedded 6T-SRAM Designed for Manufacturability With Read and Write Operation Stabilizing Circuits

Authors: Shigeki Ohbayashi, Makoto Yabuuchi, Koji Nii, Yasumasa Tsukamoto, Susumu Imaoka, Yuji Oda, Tsutomu Yoshihara, Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara

A 20-Gb/s Simultaneous Bidirectional Transceiver Using a Resistor-Transconductor Hybrid in 0.11-m CMOS

Authors: Yasumoto Tomita, Hirotaka Tamura, Masaya Kibune, Junji Ogawa, Kohtaroh Gotoh, Tadahiro Kuroda

A 50-Gbit/s 450-mW Full-Rate 4: 1 Multiplexer With Multiphase Clock Architecture in 0.13-m InP HEMT Technology

Authors: Toshihide Suzuki, Yoichi Kawano, Yasuhiro Nakasha, Shinji Yamaura, Tsuyoshi Takahashi, Kozo Makiyama, Tatsuya Hirose

Crosstalk Countermeasures for High-Density Inductive-Coupling Channel Array

Authors: Noriyuki Miura, Takayasu Sakurai, Tadahiro Kuroda

An 8.1-ns Column-Access 1.6-Gb/s/pin DDR3 SDRAM With an 8: 4 Multiplexed Data-Transfer Scheme

Authors: Hiroki Fujisawa, Shuichi Kubouchi, Koji Kuroki, Naohisa Nishioka, Yoshiro Riho, Hiromasa Noda, Isamu Fujii, Hideyuki Yoko, Ryuuji Takishita, Takahiro Ito, Hitoshi Tanaka, Masayuki Nakamura

The Design and Implementation of the Massively Parallel Processor Based on the Matrix Architecture

Authors: Hideyuki Noda, Masami Nakajima, Katsumi Dosaka, Kiyoshi Nakata, Motoki Higashida, Osamu Yamamoto, Katsuya Mizumoto, Tetsushi Tanizaki, Takayuki Gyohten, Yoshihiro Okuno, Hiroyuki Kondo, Yukihiko Shimazu, Kazutami Arimoto, Kazunori Saito, Toru Shimizu

A 1 Tb/s 3 W Inductive-Coupling Transceiver for 3D-Stacked Inter-Chip Clock and Data Link

Authors: Noriyuki Miura, Daisuke Mizoguchi, Mari Inoue, Kiichi Niitsu, Yoshihiro Nakagawa, Masamoto Tago, Muneo Fukaishi, Takayasu Sakurai, Tadahiro Kuroda

Introduction to the Special Issue on the 2006 IEEE International Solid-State Circuits Conference

Authors: James D. Warnock, William Bidermann, Albert van der Werf, Katsuyuki Sato

Hierarchical Power Distribution With Power Tree in Dozens of Power Domains for 90-nm Low-Power Multi-CPU SoCs

Authors: Yusuke Kanno, Hiroyuki Mizuno, Yoshihiko Yasu, Kenji Hirose, Yasuhisa Shimazaki, Tadashi Hoshi, Yujiro Miyairi, Toshifumi Ishii, Tetsuya Yamada, Takahiro Irita, Toshihiro Hattori, Kazumasa Yanagisawa, Naohiko Irie

An Organic FET SRAM With Back Gate to Increase Static Noise Margin and Its Application to Braille Sheet Display

Authors: Makoto Takamiya, Tsuyoshi Sekitani, Yusaku Kato, Hiroshi Kawaguchi, Takao Someya, Takayasu Sakurai

A Passive UHF RF Identification CMOS Tag IC Using Ferroelectric RAM in 0.35-m Technology

Authors: Hiroyuki Nakamoto, Daisuke Yamazaki, Takuji Yamamoto, Hajime Kurata, Satoshi Yamada, Kenji Mukaida, Tsuzumi Ninomiya, Takashi Ohkawa, Shoichi Masui, Kunihiko Gotoh

A 56-nm CMOS 99-mm2 8-Gb Multi-Level NAND Flash Memory With 10-MB/s Program Throughput

Authors: Ken Takeuchi, Yasushi Kameda, Susumu Fujimura, Hiroyuki Otake, Koji Hosono, Hitoshi Shiga, Yoshihisa Watanabe, Takuya Futatsuyama, Yoshihiko Shindo, Masatsugu Kojima, Makoto Iwai, Masanobu Shirakawa, Masayuki Ichige, Kazuo Hatakeyama, Shinichi Tanaka, Teruhiko Kamei, Jia-Yi Fu, Adi Cernea, Yan Li, Masaaki Higashitani, Gertjan Hemink, Shinji Sato, Ken Oowada, Shih-Chung Lee, Naoki Hayashida, Jun Wan, Jeffrey Lutze, Shouchang Tsao, Mehrdad Mofidi, Kiyofumi Sakurai, Naoya Tokiwa, Hiroko Waki, Yasumitsu Nozawa, Kazuhisa Kanazawa, Shigeo Ohshima

The list of papers published before 2007 is not available on dblp: IEEE Journal of Solid-State Circuits. Please use IEEE Xplore to find the papers, which are not allowed to be listed here.