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Highly contributed researchers

In recent 10 years: Kazuteru Namba (8)

Nei Kato (5) / Naofumi Homma (4)

Since 1957: Hideo Fujiwara (18) / Tsutomu Sasao (18)

Kozo Kinoshita (16) / Naofumi Takagi (15) / Shuzo Yajima (13)

Statistics

Fast Modular Arithmetic on the Kalray MPPA-256 Processor for an Energy-Efficient Implementation of ECM

Authors: Masahiro Ishii, Jrmie Detrey, Pierrick Gaudry, Atsuo Inomata, Kazutoshi Fujikawa

Routing or Computing? The Paradigm Shift Towards Intelligent Computer Network Packet Transmission Based on Deep Learning

Authors: Bomin Mao, Zubair Md. Fadlullah, Fengxiao Tang, Nei Kato, Osamu Akashi, Takeru Inoue, Kimihiro Mizutani

Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers

Authors: Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura

Formal Approach for Verifying Galois Field Arithmetic Circuits of Higher Degrees

Authors: Rei Ueno, Naofumi Homma, Yukihiro Sugawara, Takafumi Aoki

Disaggregation and Sharing of I/O Devices in Cloud Data Centers

Authors: Jun Suzuki, Yoichi Hidaka, Junichi Higuchi, Yuki Hayashi, Masaki Kan, Takashi Yoshikawa

GPUvm: GPU Virtualization at the Hypervisor

Authors: Yusuke Suzuki, Shinpei Kato, Hiroshi Yamada, Kenji Kono

A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories

Authors: Wei Wei, Kazuteru Namba, Yong-Bin Kim, Fabrizio Lombardi

A Novel Coding Scheme for Secure Communications in Distributed RFID Systems

Authors: Kazuya Sakai, Min-Te Sun, Wei-Shinn Ku, Ten-Hwang Lai

Energy Minimization in Multi-Task Software-Defined Sensor Networks

Authors: Deze Zeng, Peng Li, Song Guo, Toshiaki Miyazaki, Jiankun Hu, Yong Xiang

Parallel Decodable Two-Level Unequal Burst Error Correcting Codes

Authors: Kazuteru Namba and Fabrizio Lombardi

Automatic High-Level Data-Flow Synthesis and Optimization of Polynomial Datapaths Using Functional Decomposition

Authors: Samaneh Ghandali, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi

Address Scrambling and Data Inversion Techniques for Yield Enhancement of NROM-Based ROMs

Authors: Shyue-Kung Lu, Tsu-Lin Li, Masaki Hashizume, Jiann-Liang Chen

Software Implementation of an Attribute-Based Encryption Scheme

Authors: Eric Zavattoni, Luis J. Dominguez Perez, Shigeo Mitsunari, Ana H. Snchez-Ramrez, Tadanori Teruya, Francisco Rodrguez-Henrquez

High-Throughput Compact Delay-Insensitive Asynchronous NoC Router

Authors: Naoya Onizawa, Atsushi Matsumoto, Tomoyoshi Funazaki, Takahiro Hanyu

3D NoC with Inductive-Coupling Links for Building-Block SiPs

Authors: Yasuhiro Take, Hiroki Matsutani, Daisuke Sasaki, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano

Elliptic-Curve-Based Security Processor for RFID

Authors: Yong Ki Lee, Kazuo Sakiyama, Lejla Batina, Ingrid Verbauwhede

Algorithms and Arithmetic Operators for Computing the etaT Pairing in Characteristic Three

Authors: Jean-Luc Beuchat, Nicolas Brisebarre, Jrmie Detrey, Eiji Okamoto, Masaaki Shirase, Tsuyoshi Takagi

A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip

Authors: rika F. Cota, Fernanda Gusmo de Lima Kastensmidt, Maico Cassel, Marcos Herve, Pedro Almeida, Paulo Meirelles, Alexandre M. Amory, Marcelo Lubaszewski

Short-Memory Scalar Multiplication for Koblitz Curves

Authors: Camille Vuillaume, Katsuyuki Okeya, Tsuyoshi Takagi

Bipartite Modular Multiplication Method

Authors: Marcelo E. Kaihara and Naofumi Takagi

Condition Adaptation in Synchronous Consensus

Authors: Taisuke Izumi and Toshimitsu Masuzawa

On the Prediction of Java Object Lifetimes

Authors: Hajime Inoue, Darko Stefanovic, Stephanie Forrest

Average Path Length of Binary Decision Diagrams

Authors: Jon T. Butler, Tsutomu Sasao, Munehiro Matsuura

A Hardware Algorithm for Modular Multiplication/Division

Authors: Marcelo E. Kaihara and Naofumi Takagi

Parallel Decoding Cyclic Burst Error Correcting Codes

Authors: Ganesan Umanesan and Eiji Fujiwara

Streaming BDD Manipulation

Author: Shin-ichi Minato

A Method for Compressing Test Data Based on Burrows-Wheeler Transformation

Authors: Takahiro J. Yamaguchi, Dong Sam Ha, Masahiro Ishida, Tadahiro Ohmi

ROC-1: Hardware Support for Recovery-Oriented Computing

Authors: David L. Oppenheimer, Aaron B. Brown, James Beck, Daniel Hettena, Jon Kuroda, Noah Treuhaft, David A. Patterson, Katherine A. Yelick

Lookahead Scheduling Requests for Multisize Page Caching

Authors: Jun Kiniwa, Toshio Hamada, Daisuke Mizoguchi

Worst and Best Irredundant Sum-of-Products Expressions

Authors: Tsutomu Sasao and Jon T. Butler

A Fast Algorithm for Multiplicative Inversion in GF(2m) Using Normal Basis

Authors: Naofumi Takagi, Jun-ichi Yoshiki, Kazuyoshi Takagi

Fast Gossiping on Mesh-Bus Computers

Authors: Satoshi Fujita and Masafumi Yamashita

Hierarchical Execution to Speed Up Pipeline Interlock in Mainframe Computers

Authors: Yooichi Shintani, Toru Shonai, Hiroshi Kurokawa, Kazunori Kuriyama, Akira Yamaoka

Author's Reply

Authors: Shoji Kawahito, Makoto Ishida, Tasuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi

Probability to Achieve TSC Goal

Authors: Jien-Chung Lo and Eiji Fujiwara

Aliasing Error for a Mask ROM Built-In Self-Test

Authors: Kazuhiko Iwasaki and Shigeo Nakamura

On Polynomial-Time Testable Combinational Circuits

Authors: Nageswara S. V. Rao and Shunichi Toida

High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits

Authors: Shoji Kawahito, Makoto Ishida, Tetsuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi

Accurate Ronding Scheme for the Newton-Raphson Method Using Redundant Binary Representation

Authors: Hideyuki Kabuo, Takashi Taniguchi, Akira Miyoshi, Hitoshi Yamashita, Miki Urano, Hisakazu Edamatsu, Shigeo Kuninobu

Availability of k-Coterie

Authors: Hirotsugu Kakugawa, Satoshi Fujita, Masafumi Yamashita, Tadashi Ae

Minimization of AND-EXOR Expressions Using Rewrite Rules

Authors: Daniel Brand and Tsutomu Sasao

Notes on Multiple Input Signature Analysis

Authors: Tiko Kameda, Slawomir Pilarski, Andr Ivanov

The Via Minimization Problem is NP-Complete

Authors: Nicholas J. Naclerio, Sumio Masuda, Kazuo Nakajima

The Transduction Method-Design of Logic Networks Based on Permissible Functions

Authors: Saburo Muroga, Yahiko Kambayashi, Hung Chi Lai, Jay Niel Culliney

The CrossoverNet LAN System Using an Intelligent Head-End

Authors: Senro Saito, Hiroyuki Yoshida, Tosiyasu L. Kunii

An Adaptive Hierarchical Routing Protocol

Authors: Wei-Tek Tsai, C. V. Ramamoorthy, Wei Kang Tsai, Osamu Nishiguchi

The Stack Growth Function: Cache Line Reference Models

Authors: Makoto Kobayashi and Myron H. MacDougall

Tolerance of Double-Loop Computer Networks to Multinode Failures

Authors: Hiroshi Masuyama and Tetsuo Ichimori

K-Way Bitonic Sort

Authors: Toshio Nakatani, Shing-Tsaan Huang, Bruce W. Arden, Satish K. Tripathi

Lower Bounds on Crosspoints in Concentrators

Authors: Shinji Nakamura and Gerald M. Masson

The Parallel Enumeration Sorting Scheme for VLSI

Authors: Hiroto Yasuura, Naofumi Takagi, Shuzo Yajima

PICCOLO Logic for a Picture Database Computer and Its Implementation

Authors: Kazunori Yamaguchi and Tosiyasu L. Kunii

Deadlock-Free Systems for a Bounded Number of Processes

Authors: Toshihide Ibaraki and Tsunehiko Kameda

A Task Allocation Model for Distributed Computing Systems

Authors: Perng-Yi Richard Ma, Edward Y. S. Lee, Masahiro Tsuchiya

A Design of Programmable Logic Arrays with Universal Tests

Authors: Hideo Fujiwara and Kozo Kinoshita

A Layout System for the Random Logic Portion of an MOS LSI Chip

Authors: Isao Shirakawa, Noboru Okuda, Takashi Harada, Sadahiro Tani, Hiroshi Ozaki

Optimization of Microprograms

Authors: Mario Tokoro, Euji Tamura, Takashi Takizuka

Design to Minimize Diameter on Building-Block Network

Authors: Makoto Imase and Masaki Itoh

Optimal Layout of CMOS Functional Arrays

Authors: Takao Uehara and William M. van Cleemput

Rewritable Progammable Logic Array of Current Mode Logic

Authors: Mamoru Tanaka, Shinji Ozawa, Shinsaku Mori

On Minimal Test Sets for Locating Single Link Failures in Networks

Authors: Toshihide Ibaraki, Tsunehiko Kameda, Shunichi Toida

An Approach to Gate Assignment and Module Placement for Printed Wiring Boards

Authors: Ikuo Nishioka, Takuji Kurimoto, Seiji Yamamoto, Toru Chiba, Isao Shirakawa, Hiroshi Ozaki

A Dynamically Microprogammable Computer with Low-Level Parallelism

Authors: Hiroshi Hagiwara, Shinji Tomita, Shigeru Oyanagi, Kiyoshi Shibayama

A Symmetric Cosine Transform

Author: Hideo Kitajima

The Development of a Bubble Memory Controller for Low-Cost File Use

Authors: Yuzo Kita, Noboru Yamaguchi, Mamoru Sugie, Shigeru Yoshizawa

An NMOS Microcomputer Peripheral Interface Unit Incorporating an Analog-to-Digital Converter

Authors: Tsuneo Funabashi, Katsuaki Takagi, Toshiro Tsukada, Hideo Nakamura, Michio Hara

Nonparametric Learning Without a Teacher Based on Mode Estimation

Authors: Riichiro Mizoguchi and Masamichi Shimura

Toward Optimization of Horizontal Microprograms

Authors: Masahiro Tsuchiya and Mario J. Gonzalez

A Note on the Linear Space Automata Stability Problem

Authors: Kazue Sugino, Yasuyoshi Inagaki, Teruo Fukumura

On Magnetic Bubble Logic Circuits

Authors: Kozo Kinoshita, Tsutomu Sasao, Jun Matsuda

An Approach to Unsupervised Learning Classification

Authors: Riichiro Mizoguchi and Masamichi Shimura

A New Voltage to Frequency Converter

Authors: Keiji Taniguchi and Takanori Sakai

An Approach to the Diagnosability Analysis of a System

Authors: F. J. Allan, Tiko Kameda, S. Toida

Easily Testable Sequential Machines with Extra Inputs

Authors: Hideo Fujiwara, Yoich Nagao, Tsutomu Sasao, Kozo Kinoshita

The Range of Logical Flexibility of Tree Networks

Authors: Akira Maruoka and Namio Honda

Macro E-Nets for Representation of Parallel Systems

Authors: Jerre D. Noe and Gary J. Nutt

The Parallel Evaluation of Arithmetic Expressions Without Division

Authors: Richard Brent, Daniel Kuck, Kiyoshi Maruyama

Logical Networks of Flexible Cells

Authors: Akira Maruoka and Namio Honda

General Division in the Symmetric Residue Number System

Authors: Eisuke Kinoshita, Hideo Kosako, Yoshiaki Kojima

Realization of Fail-Safe Sequential Machines by Using a k-out-of-n Code

Authors: Yoshihiro Tohma, Yasuyoshi Ohyama, Ryozo Sakai

Computer Diagnosis Using the Blocking Gate Approach

Authors: Chittoor V. Ramamoorthy and Wataru Mayeda

N-Fail-Safe Logical Systems

Authors: Tadao Takaoka and Hisashi Mine

Failure-Tolerant Sequential Machines with Past Information

Authors: Yoshihiro Tohma and Susumu Aoyagi

Failsafe Logic Nets

Authors: Nobuki Tokura, Tadao Kasami, Akihiro Hashimoto

A Property of N-Graphs

Authors: Akihiro Hashimoto and Kohei Noshita

Synthesis of Networks with a Minimum Number of Negative Gates

Authors: Toshihide Ibaraki and Saburo Muroga

The ILLIAC IV Computer

Authors: George H. Barnes, Richard M. Brown, Maso Kato, David J. Kuck, Daniel L. Slotnick, Richard A. Stokes

Authors' Reply3

Authors: Hisashi Mine and Yoshihaki Koga

On Autonomous Logic Nets of Threshold Elements

Authors: Shuzo Yajima, Toshihide Ibaraki, I. Kawano

Lower Bound of the Number of Threshold Functions

Authors: Saburo Muroga and Iwao Toda

Woven Wire Memory for NDRO System

Authors: H. Maeda, A. Matsushita, M. Takashima

A Lower Bound of the Number of Threshold Functions

Authors: Shuzo Yajima and Toshihide Ibaraki

A Learning Network Using Adaptive Threshold Elements

Authors: Haruhisa Ishida and Robert M. Stewart Jr.

Bilateral Switching Using Nonsymmetric Elements

Authors: Masanao Aoki and Gerald Estrin

Regular Expressions and State Graphs for Automata

Authors: Robert McNaughton and Hisao Yamada

Esaki Diode High-Speed Logical Circuits

Authors: Eiichi Goto, Kenro Murata, Kisaburo Nakazawa, Keisuke Nakagawa, Tohru Moto-Oka, Yasushi Miatsu-Oka, Yoshihiro Ishibashi, Haruhisa Ishida, Takashi Soma, Eiiti Wada

System Organization of a Multiple-Cockpit Digital Operational Flight Trainer

Authors: Harry J. Gray Jr., Hiroshi H. Nishino, Alvin L. Vivatson

The Parametron Digital Computer MUSASINO-1

Authors: Saburo Muroga and Kensuke Takashima

A New Diode Function Generator

Authors: T. Miura, Hiroshi Amemiya, T. Numakura