IEEE Transactions on Computers Papers Published by Researchers in Japan

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Highly contributed researchers

In recent 10 years: Kazuteru Namba (7)

Nozomu Togawa (5) / Nei Kato (5) / Naofumi Homma (4)

Since 1957: Hideo Fujiwara (18) / Tsutomu Sasao (18)

Kozo Kinoshita (16) / Naofumi Takagi (15) / Shuzo Yajima (13)

Statistics

2023

Spin-Variable Reduction Method for Handling Linear Equality Constraints in Ising Machines

Authors: Tatsuhiko Shirai and Nozomu Togawa

Multi-Spin-Flip Engineering in an Ising Machine

Authors: Tatsuhiko Shirai and Nozomu Togawa

R-HTDetector: Robust Hardware-Trojan Detection Based on Adversarial Training

Authors: Kento Hasegawa, Seira Hidano, Kohei Nozawa, Shinsaku Kiyomoto, Nozomu Togawa

2022

VisualNet: An End-to-End Human Visual System Inspired Framework to Reduce Inference Latency of Deep Neural Networks

Authors: Tianchen Wang, Jiawei Zhang, Jinjun Xiong, Song Bian, Zheyu Yan, Meiping Huang, Jian Zhuang, Takashi Sato, Xiaowei Xu, Yiyu Shi

Hybrid Annealing Method Based on subQUBO Model Extraction With Multiple Solution Instances

Authors: Yuta Atobe, Masashi Tawada, Nozomu Togawa

Enabling Homomorphically Encrypted Inference for Large DNN Models

Authors: Guillermo Lloret-Talavera, Marc Jord, Harald Servat, Fabian Boemer, Chetan Chauhan, Shigeki Tomishima, Nilesh N. Shah, Antonio J. Pea

PyQUBO: Python Library for Mapping Combinatorial Optimization Problems to QUBO Form

Authors: Mashiyat Zaman, Kotaro Tanahashi, Shu Tanaka

How to Reduce the Bit-Width of an Ising Model by Adding Auxiliary Spins

Authors: Daisuke Oku, Masashi Tawada, Shu Tanaka, Nozomu Togawa

2021

OPTWEB: A Lightweight Fully Connected Inter-FPGA Network for Efficient Collectives

Authors: Kenji Mizutani, Hiroshi Yamaguchi, Yutaka Urino, Michihiro Koibuchi

2020

A Neural Network-Based On-Device Learning Anomaly Detector for Edge Devices

Authors: Mineto Tsukada, Masaaki Kondo, Hiroki Matsutani

High Throughput/Gate AES Hardware Architectures Based on Datapath Compression

Authors: Rei Ueno, Naofumi Homma, Sumio Morioka, Noriyuki Miura, Kohei Matsuda, Makoto Nagata, Shivam Bhasin, Yves Mathieu, Tarik Graba, Jean-Luc Danger

Footprint-Based DIMM Hotplug

Authors: Shinobu Miwa, Masaya Ishihara, Hayato Yamaki, Hiroki Honda, Martin Schulz

2019

Improved Division Property Based Cube Attacks Exploiting Algebraic Properties of Superpoly

Authors: Yonglin Hao, Takanori Isobe, Lin Jiao, Chaoyun Li, Willi Meier, Yosuke Todo, Qingju Wang

An Absorbing Markov Chain Based Model to Solve Computation and Communication Tradeoff in GPU-Accelerated MDRUs for Safety Confirmation in Disaster Scenarios

Authors: Bomin Mao, Fengxiao Tang, Zubair Md. Fadlullah, Nei Kato

Concurrent Error Detectable Carry Select Adder with Easy Testability

Authors: Nobutaka Kito and Naofumi Takagi

Tackling Biased PUFs Through Biased Masking: A Debiasing Method for Efficient Fuzzy Extractor

Authors: Rei Ueno, Manami Suzuki, Naofumi Homma

Value Iteration Architecture Based Deep Learning for Intelligent Routing Exploiting Heterogeneous Computing Platforms

Authors: Zubair Md. Fadlullah, Bomin Mao, Fengxiao Tang, Nei Kato

Coding for Write Latency Reduction in a Multi-Level Cell (MLC) Phase Change Memory (PCM)

Authors: Kazuteru Namba and Fabrizio Lombardi

2018

Cube Attacks on Non-Blackbox Polynomials Based on Division Property

Authors: Yosuke Todo, Takanori Isobe, Yonglin Hao, Willi Meier

A Single and Adjacent Error Correction Code for Fast Decoding of Critical Bits

Authors: Kazuteru Namba and Fabrizio Lombardi

Cloudlets Activation Scheme for Scalable Mobile Edge Computing with Transmission Power Control and Virtual Machine Migration

Authors: Tiago Gama Rodrigues, Katsuya Suto, Hiroki Nishiyama, Nei Kato, Katsuhiro Temma

Tight Bounds of Differentially and Linearly Active S-Boxes and Division Property of Lilliput

Authors: Yu Sasaki and Yosuke Todo

Efficient Data-Allocation Scheme for Eliminating Garbage Collection During Analysis of Big Graphs Stored in NAND Flash Memory

Authors: Hiroshi Uchigaito, Seiji Miura, Takumi Nito

2017

Fast Modular Arithmetic on the Kalray MPPA-256 Processor for an Energy-Efficient Implementation of ECM

Authors: Masahiro Ishii, Jrmie Detrey, Pierrick Gaudry, Atsuo Inomata, Kazutoshi Fujikawa

Routing or Computing? The Paradigm Shift Towards Intelligent Computer Network Packet Transmission Based on Deep Learning

Authors: Bomin Mao, Zubair Md. Fadlullah, Fengxiao Tang, Nei Kato, Osamu Akashi, Takeru Inoue, Kimihiro Mizutani

Hybrid Method for Minimizing Service Delay in Edge Cloud Computing Through VM Migration and Transmission Power Control

Authors: Tiago Gama Rodrigues, Katsuya Suto, Hiroki Nishiyama, Nei Kato

Scalable Networks-on-Chip with Elastic Links Demarcated by Decentralized Routers

Authors: Ryota Yasudo, Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tadao Nakamura

Formal Approach for Verifying Galois Field Arithmetic Circuits of Higher Degrees

Authors: Rei Ueno, Naofumi Homma, Yukihiro Sugawara, Takafumi Aoki

2016

Parallel Decodable Multi-Level Unequal Burst Error Correcting Codes for Memories of Approximate Systems

Authors: Kazuteru Namba and Fabrizio Lombardi

Disaggregation and Sharing of I/O Devices in Cloud Data Centers

Authors: Jun Suzuki, Yoichi Hidaka, Junichi Higuchi, Yuki Hayashi, Masaki Kan, Takashi Yoshikawa

GPUvm: GPU Virtualization at the Hypervisor

Authors: Yusuke Suzuki, Shinpei Kato, Hiroshi Yamada, Kenji Kono

Multicast-Based Testing and Thermal-Aware Test Scheduling for 3D ICs with a Stacked Network-on-Chip

Authors: Dong Xiang, Krishnendu Chakrabarty, Hideo Fujiwara

Single Multiscale-Symbol Error Correction Codes for Multiscale Storage Systems

Authors: Kazuteru Namba and Fabrizio Lombardi

A Novel Scheme for Tolerating Single Event/Multiple Bit Upsets (SEU/MBU) in Non-Volatile Memories

Authors: Wei Wei, Kazuteru Namba, Yong-Bin Kim, Fabrizio Lombardi

A Novel Coding Scheme for Secure Communications in Distributed RFID Systems

Authors: Kazuya Sakai, Min-Te Sun, Wei-Shinn Ku, Ten-Hwang Lai

2015

Energy Minimization in Multi-Task Software-Defined Sensor Networks

Authors: Deze Zeng, Peng Li, Song Guo, Toshiaki Miyazaki, Jiankun Hu, Yong Xiang

Parallel Decodable Two-Level Unequal Burst Error Correcting Codes

Authors: Kazuteru Namba and Fabrizio Lombardi

Non-Binary Orthogonal Latin Square Codes for a Multilevel Phase Charge Memory (PCM)

Authors: Kazuteru Namba and Fabrizio Lombardi

Automatic High-Level Data-Flow Synthesis and Optimization of Polynomial Datapaths Using Functional Decomposition

Authors: Samaneh Ghandali, Bijan Alizadeh, Masahiro Fujita, Zainalabedin Navabi

Address Scrambling and Data Inversion Techniques for Yield Enhancement of NROM-Based ROMs

Authors: Shyue-Kung Lu, Tsu-Lin Li, Masaki Hashizume, Jiann-Liang Chen

Software Implementation of an Attribute-Based Encryption Scheme

Authors: Eric Zavattoni, Luis J. Dominguez Perez, Shigeo Mitsunari, Ana H. Snchez-Ramrez, Tadanori Teruya, Francisco Rodrguez-Henrquez

2014

Toward Formal Design of Practical Cryptographic Hardware Based on Galois Field Arithmetic

Authors: Naofumi Homma, Kazuya Saito, Takafumi Aoki

High-Throughput Compact Delay-Insensitive Asynchronous NoC Router

Authors: Naoya Onizawa, Atsushi Matsumoto, Tomoyoshi Funazaki, Takahiro Hanyu

3D NoC with Inductive-Coupling Links for Building-Block SiPs

Authors: Yasuhiro Take, Hiroki Matsutani, Daisuke Sasaki, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano

Protein Sequence Pattern Matching: Leveraging Application Specific Hardware Accelerators

Authors: Sagi Manole, Amit Golander, Shlomo Weiss

2013

Dynamic Bit Encoding for Privacy Protection against Correlation Attacks in RFID Backward Channel

Authors: Kazuya Sakai, Wei-Shinn Ku, Roger Zimmermann, Min-Te Sun

Enhancing Performance of Random Testing through Markov Chain Monte Carlo Methods

Authors: Bo Zhou, Hiroyuki Okamura, Tadashi Dohi

2011

Test Sets for Robust Path Delay Fault Testing on Two-Rail Logic Circuits

Authors: Kazuteru Namba and Hideo Ito

A Branch-and-Bound Algorithm for Solving the Multiprocessor Scheduling Problem with Improved Lower Bounding Techniques

Author: Satoshi Fujita

Prediction Router: A Low-Latency On-Chip Router Architecture with Multiple Predictors

Authors: Hiroki Matsutani, Michihiro Koibuchi, Hideharu Amano, Tsutomu Yoshinaga

Fast Architectures for the \eta_T Pairing over Small-Characteristic Supersingular Elliptic Curves

Authors: Jean-Luc Beuchat, Jrmie Detrey, Nicolas Estibals, Eiji Okamoto, Francisco Rodrguez-Henrquez

2010

Stability-Optimized Time Adjustment for a Networked Computer Clock

Author: Takao Yamashita

Comparative Power Analysis of Modular Exponentiation Algorithms

Authors: Naofumi Homma, Atsushi Miyamoto, Takafumi Aoki, Akashi Satoh, Adi Shamir

Modular Model Checking of Large Asynchronous Designs with Efficient Abstraction Refinement

Authors: Hao Zheng, Haiqiong Yao, Tomohiro Yoneda

2009

Orchestrating Horizontal Parallelism and Vertical Instruction Packing of Programs to Improve System Overall Efficiency

Authors: Hai Lin and Yunsi Fei

High-Performance Hardware Architectures for Galois Counter Mode

Authors: Akashi Satoh, Takeshi Sugawara, Takafumi Aoki

Complexities of Graph-Based Representations for Elementary Functions

Authors: Shinobu Nagayama and Tsutomu Sasao

2008

A Systematic Approach for Designing Redundant Arithmetic Adders Based on Counter Tree Diagrams

Authors: Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi

Algorithms and Arithmetic Operators for Computing the etaT Pairing in Characteristic Three

Authors: Jean-Luc Beuchat, Nicolas Brisebarre, Jrmie Detrey, Eiji Okamoto, Masaaki Shirase, Tsuyoshi Takagi

Elliptic-Curve-Based Security Processor for RFID

Authors: Yong Ki Lee, Kazuo Sakiyama, Lejla Batina, Ingrid Verbauwhede

A High-Fault-Coverage Approach for the Test of Data, Control and Handshake Interconnects in Mesh Networks-on-Chip

Authors: rika F. Cota, Fernanda Gusmo de Lima Kastensmidt, Maico Cassel, Marcos Herv, Pedro Almeida, Paulo Meirelles, Alexandre M. Amory, Marcelo Lubaszewski

Short-Memory Scalar Multiplication for Koblitz Curves

Authors: Camille Vuillaume, Katsuyuki Okeya, Tsuyoshi Takagi

Bipartite Modular Multiplication Method

Authors: Marcelo E. Kaihara and Naofumi Takagi

2007

Communication Links for Distributed Quantum Computation

Authors: Rodney Van Meter, Kae Nemoto, W. J. Munro

Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST

Authors: Dong Xiang, Mingjing Chen, Hideo Fujiwara

Guest Editors' Introduction: Special Section on Emergent Systems, Algorithms and Architectures for Speech-Based Human-Machine Interaction

Authors: Rodrigo Capobianco Guido, Li Deng, Shoji Makino

Multicore Curve-Based Cryptoprocessor with Reconfigurable Modular Arithmetic Logic Units over GF(2n)

Authors: Kazuo Sakiyama, Lejla Batina, Bart Preneel, Ingrid Verbauwhede

Incorporating Knowledge Sources Into a Statistical Acoustic Model for Spoken Language Communication Systems

Authors: Sakriani Sakti, Konstantin Markov, Satoshi Nakamura

Numerical Function Generators Using LUT Cascades

Authors: Tsutomu Sasao, Shinobu Nagayama, Jon T. Butler

An Integrated Memory Array Processor for Embedded Image Recognition Systems

Authors: Shorin Kyo, Shin'ichiro Okazaki, Tamio Arai

Modified Low-Density MDS Array Codes for Tolerating Double Disk Failures in Disk Arrays

Authors: Hachiro Fujita and Kohichi Sakaniwa

Reconfigured Scan Forest for Test Application Cost, Test Data Volume, and Test Power Reduction

Authors: Dong Xiang, Kaiwei Li, Jiaguang Sun, Hideo Fujiwara

Adaptive Resource Allocation Control for Fair QoS Management

Authors: Fumiko Harada, Toshimitsu Ushio, Yukikazu Nakamoto

2006

On the Prediction of Java Object Lifetimes

Authors: Hajime Inoue, Darko Stefanovic, Stephanie Forrest

Condition Adaptation in Synchronous Consensus

Authors: Taisuke Izumi and Toshimitsu Masuzawa

Analysis of Fractional Window Recoding Methods and Their Application to Elliptic Curve Cryptosystems

Authors: Katja Schmidt-Samoa, Olivier Semay, Tsuyoshi Takagi

2005

Average Path Length of Binary Decision Diagrams

Authors: Jon T. Butler, Tsutomu Sasao, Munehiro Matsuura

Genetic Approach to Minimizing Energy Consumption of VLSI Processors Using Multiple Supply Voltages

Authors: Masanori Hariyama, Tetsuya Aoyama, Michitaka Kameyama

A Hardware Algorithm for Modular Multiplication/Division

Authors: Marcelo E. Kaihara and Naofumi Takagi

Parallel Decoding Cyclic Burst Error Correcting Codes

Authors: Ganesan Umanesan and Eiji Fujiwara

2004

A Combined Approach to High-Level Synthesis for Dynamically Reconfigurable Systems

Authors: Mahmoud Mribout and Masato Motomura

Virtualizing Network I/O on End-Host Operating System: Operating System Support forNetwork Control and Resource Protection

Authors: Takashi Okumura and Daniel Moss

Universal Delay-Insensitive Circuits with Bidirectional and Buffering Lines

Authors: Jia Lee, Ferdinand Peper, Susumu Adachi, Kenichi Morita

A General Stochastic Model for Dynamic Locking in Database Systems

Authors: Yong Jiang, Jie Li, Shoichi Nishimura

A Class of M-Ary Asymmetric Symbol Error Correcting Codes for Data Entry Devices

Authors: Haruhiko Kaneko and Eiji Fujiwara

2003

Nonscan Design for Testability for Synchronous Sequential Circuits Based on Conflict Resolution

Authors: Dong Xiang, Yi Xu, Hideo Fujiwara

(t, k)-Diagnosable System: A Generalization of the PMC Models

Authors: Toru Araki and Yukio Shibata

A Class of Random Multiple Bits in a Byte Error Correcting and Single Byte Error Detecting (S_t/b EC-S_bED) Codes

Authors: Ganesan Umanesan and Eiji Fujiwara

A Scalable Dual-Field Elliptic Curve Cryptographic Processor

Authors: Akashi Satoh and Kohji Takano

2002

Streaming BDD Manipulation

Author: Shin-ichi Minato

A Method for Compressing Test Data Based on Burrows-Wheeler Transformation

Authors: Takahiro J. Yamaguchi, Dong Sam Ha, Masahiro Ishida, Tadahiro Ohmi

ROC-1: Hardware Support for Recovery-Oriented Computing

Authors: David L. Oppenheimer, Aaron B. Brown, James Beck, Daniel Hettena, Jon Kuroda, Noah Treuhaft, David A. Patterson, Katherine A. Yelick

2001

A Note on Complexity of OBDD Composition and Efficiency of Partitioned-OBDDs over OBDDs

Authors: Jawahar Jain, Ingo Wegener, Masahiro Fujita

Lookahead Scheduling Requests for Multisize Page Caching

Authors: Jun Kiniwa, Toshio Hamada, Daisuke Mizoguchi

Worst and Best Irredundant Sum-of-Products Expressions

Authors: Tsutomu Sasao and Jon T. Butler

A Fast Algorithm for Multiplicative Inversion in GF(2m) Using Normal Basis

Authors: Naofumi Takagi, Jun-ichi Yoshiki, Kazuyoshi Takagi

2000

Neighborhood Information Dissemination in the Star Graph

Author: Satoshi Fujita

RT-CRM: Real-Time Channel-Based Reflective Memory

Authors: Chia Shen and Ichiro Mizunuma

A VLSI Algorithm for Computing the Euclidean Norm of a 3D Vector

Authors: Naofumi Takagi and Seiji Kuwahara

A New Class of Sequential Circuits with Combinational Test Generation Complexity

Author: Hideo Fujiwara

Fault-Tolerant Processor Arrays Based on the 1½-Track Switches with Flexible Spare Distributions

Authors: Tadayoshi Horita and Itsuo Takanami

Fault-Tolerant Processor Arrays Using Additional Bypass Linking Allocated by Graph-Node Coloring

Author: Nobuo Tsuda

Discrete Interval Truth Values Logic and Its Application

Authors: Noboru Takagi and Kyoichi Nakashima

1999

A Fault-Tolerant Broadcast Scheme in the Star Graph under the Single-Port, Half-Duplex Communication Model

Author: Satoshi Fujita

Improving the Availability of Mutual Exclusion Systems on Incomplete Networks

Authors: Takashi Harada and Masafumi Yamashita

The GRD Chip: Genetic Reconfiguration of DSPs for Neural Network Processing

Authors: Masahiro Murakawa, Shuji Yoshizawa, Isamu Kajitani, Xin Yao, Nobuki Kajihara, Masaya Iwata, Tetsuya Higuchi

Augmenting Loop Tiling with Data Alignment for Improved Cache Performance

Authors: Preeti Ranjan Panda, Hiroshi Nakamura, Nikil D. Dutt, Alexandru Nicolau

A Gracefully Degrading Massively Parallel System Using the BSP Model, and Its Evaluation

Authors: Andreas Savva and Takashi Nanya

A High-Speed Reduced-Size Adder Under Left-to-Right Input Arrival

Authors: Naofumi Takagi and Takashi Horiyama

Improving Design Dependability by Exploiting an Open Model-Based Specification

Authors: Aki W. Tomita and Ken Sakamura

1998

Optimal Two-Level Unequal Error Control Codes for Computer Systems

Authors: Eiji Fujiwara, Tepparit Ritthongpitak, Masato Kitakami

Powering by a Table Look-Up and a Multiplication with Operand Modification

Author: Naofumi Takagi

CAM2: A Highly-Parallel Two-Dimensional Cellular Architecture

Authors: Takeshi Ikenaga and Takeshi Ogura

Load Balancing Problems for Multiclass Jobs in Distributed/Parallel Computer Systems

Authors: Jie Li and Hisao Kameda

A Learning Multiple-Valued Logic Network: Algebra, Algorithm, and Applications

Authors: Zheng Tang and Okihiko Ishizuka

A Hierarachical Adaptive Distributed System-Level Diagnosis Algorithm

Authors: Elias Procpio Duarte Jr. and Takashi Nanya

1997

O(n)-Depth Modular Exponentiation Circuit Algorithm

Authors: Takafumi Hamano, Naofumi Takagi, Shuzo Yajima, Franco P. Preparata

Easily Testable Realizations for Generalized Reed-Muller Expressions

Author: Tsutomu Sasao

Average an Worst Case Number of Nodes in Decision Diagrams of Symmetric Multiple-Valued Functions

Authors: Jon T. Butler, David S. Herscovici, Tsutomu Sasao, Robert J. Barton III

Efficient Initial Approximation for Multiplicative Division and Square Root by a Multiplication with Operand Modification

Authors: Masayuki Ito, Naofumi Takagi, Shuzo Yajima

A Residue Arithmetic Extension for Reliable Scientific Computation

Authors: Eisuke Kinoshita and Ki-Ja Lee

A Class of Error Control Codes for Byte Organized Memory Systems -SbEC-(Sb+S)ED Codes-

Authors: Mitsuru Hamada and Eiji Fujiwara

1996

Fault-Tolerant Design of Neural Networks for Solving Optimization Problems

Authors: Yoshihiro Tohma and Yoichi Koyanagi

Fast Gossiping on Mesh-Bus Computers

Authors: Satoshi Fujita and Masafumi Yamashita

Author's Reply

Authors: Shoji Kawahito, Makoto Ishida, Tasuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi

Hierarchical Execution to Speed Up Pipeline Interlock in Mainframe Computers

Authors: Yooichi Shintani, Toru Shonai, Hiroshi Kurokawa, Kazunori Kuriyama, Akira Yamaoka

Probability to Achieve TSC Goal

Authors: Jien-Chung Lo and Eiji Fujiwara

Aliasing Error for a Mask ROM Built-In Self-Test

Authors: Kazuhiko Iwasaki and Shigeo Nakamura

1995

On the Maximum Value of Aliasing Probabilities for Single Input Signature Registers

Authors: Shou-ping Feng, Toru Fujiwara, Tadao Kasami, Kazuhiko Iwasaki

Hypercube Multiprocessors with Bus Connections for Improving Communication Performance

Author: Tsutomu Ishikawa

A Performance and Cost Analysis of Applying Superscalar Method to Mainframe Computers

Authors: Yooichi Shintani, Kiyoshi Inoue, Eiki Kamada, Toru Shonai

Stochastic Models for Performance Analysis of Database Recovery Control

Authors: Paulo B. Ges and Ushio Sumita

Fast Evaluation of the Elementary Functions in Single Precision

Authors: Weng-Fai Wong and Eiichi Goto

A Design of Reed-Solomon Decoder with Systolic Array Structure

Authors: Keiichi Iwamura, Yasunori Dohi, Hideki Imai

1994

On Polynomial-Time Testable Combinational Circuits

Authors: Nageswara S. V. Rao and Shunichi Toida

A Highly OR-Parallel Inference Machine (Multi-ASCA) and Its Performance Evaluation: An Architecture and Its Load Balancing Algorithms

Authors: Jiro Naganuma and Takeshi Ogura

Logically Instantaneous Message Passing in Asynchronous Distributed Systems

Authors: Terunao Soneoka and Toshihide Ibaraki

Fast Hardware-Based Algorithms for Elementary Function Computations Using Rectangular Multipliers

Authors: Weng-Fai Wong and Eiichi Goto

Accurate Ronding Scheme for the Newton-Raphson Method Using Redundant Binary Representation

Authors: Hideyuki Kabuo, Takashi Taniguchi, Akira Miyoshi, Hitoshi Yamashita, Miki Urano, Hisakazu Edamatsu, Shigeo Kuninobu

High-Speed Area-Efficient Multiplier Design Using Multiple-Valued Current-Mode Circuits

Authors: Shoji Kawahito, Makoto Ishida, Tetsuro Nakamura, Michitaka Kameyama, Tatsuo Higuchi

1993

A Note on Aliasing Probability for Multiple Input Signature Analyzer

Authors: Masakatu Morii and Kazuhiko Iwasaki

Some Fundamental Properties of Multiple-Valued Kleenean Functions and Determination of Their Logic Formulas

Authors: Yutaka Hata, Kyoichi Nakashima, Kazuharu Yamato

Numerical Accuracy and Hardware Tradeoffs for CORDIC Arithmetic for Special-Purpose Processors

Authors: Kishore Kota and Joseph R. Cavallaro

Minimization of AND-EXOR Expressions Using Rewrite Rules

Authors: Daniel Brand and Tsutomu Sasao

Availability of k-Coterie

Authors: Hirotsugu Kakugawa, Satoshi Fujita, Masafumi Yamashita, Tadashi Ae

Some Codes for Correcting and Detecting Unidirectional Byte Errors

Authors: Yuichi Saitoh and Hideki Imai

Comparisons of Seven Neural Network Models on Traffic Control Problems in Multistage Interconnection Networks

Authors: Nobuo Funabiki, Yoshiyasu Takefuji, Kuo Chun Lee

Notes on Multiple Input Signature Analysis

Authors: Tiko Kameda, Slawomir Pilarski, Andr Ivanov

1992

Task Allocation for Maximizing Reliability of Distributed Computer Systems

Authors: Sol M. Shatz, Jia-Ping Wang, Masanori Goto

A Radix-4 Modular Multiplication Hardware Algorithm for Modular Exponentiation

Author: Naofumi Takagi

Overflow/Underflow-Free Floating-Point Number Representations with Self-Delimiting Variable-Length Exponent Field

Author: Hidetoshi Yokoo

Modular Multiplication Hardware Algorithms with a Redundant Representation and Their Application to RSA Cryptosystem

Authors: Naofumi Takagi and Shuzo Yajima

Cache Memories for Data Flow Machines

Author: Masaru Takesue

A Testable Design of Logic Circuits under Highly Observable Condition

Authors: Xiaoqing Wen and Kozo Kinoshita

P-Functions-Ternary Logic Functions Capable of Correcting Input Failures and Suitable for Treating Ambiguities

Authors: Yoshinori Yamamoto and Masao Mukaidono

1991

Redundant CORDIC Methods with a Constant Scale Factor for Sine and Cosine Computation

Authors: Naofumi Takagi, Tohru Asada, Shuzo Yajima

Pseudorandom Rounding for Truncated Multipliers

Authors: Nobuaki Yoshida, Eiichi Goto, Shuichi Ichikawa

A Note on t-Unidirectional Error Correcting and d(d=t)-Unidirectional Error Detecting (t-UEC and d-UED) Codes

Authors: Kohichi Sakaniwa, Tae Nam Ahn, T. R. N. Rao

Bounds on the Average Number of Products in the Minimum Sum-of-Products Expressions for Multiple-Valued Input Two-Valued Output Functions

Author: Tsutomu Sasao

SDE: Incremental Specification and Development of Communications Software

Authors: Haruhisa Ichikawa, Masaki Itoh, June Kato, Akira Takura, Masashi Shibasaki

An Integrated Approach to Design of Protocol Specifications Using Protocol Validation and Synthesis

Authors: Yoshiaki Kakuda and Hironori Saito

Strategic Testing Environment with Formal Description Techniques

Authors: Kotaro Katsuyama, Fumiaki Sato, Tetsuo Nakakawaji, Tadanori Mizuno

A User Friendly Software Environment for Protocol Synthesis

Authors: Norio Shiratori, Yaoxue Zhang, Kaoru Takahashi, Shoichi Noguchi

1990

(SM)²-II: A Large-Scale Multiprocessor for Sparse Matrix Calculations

Authors: Hideharu Amano, Taisuke Boku, Tomohiro Kudoh

Computational Complexity of Controllability/Observability Problems for Combinational Circuits

Author: Hideo Fujiwara

Fuzzy Multiple-Input Maximum and Minimum Circuits in Current Mode and Their Analyses Using Bounded-Difference Equations

Authors: Mamoru Sasaki, Takahiro Inoue, Yuji Shirai, Fumio Ueno

Analysis of Self-Stabilizing Clock Synchronization by Means of Stochastic Petri Nets

Authors: Meiliu Lu, Du Zhang, Tadao Murata

Crossing Minimization in Linear Embeddings of Graphs

Authors: Sumio Masuda, Kazuo Nakajima, Toshinobu Kashiwabara, Toshio Fujisawa

1989

The Via Minimization Problem is NP-Complete

Authors: Nicholas J. Naclerio, Sumio Masuda, Kazuo Nakajima

The Transduction Method-Design of Logic Networks Based on Permissible Functions

Authors: Saburo Muroga, Yahiko Kambayashi, Hung Chi Lai, Jay Niel Culliney

The CrossoverNet LAN System Using an Intelligent Head-End

Authors: Senro Saito, Hiroyuki Yoshida, Tosiyasu L. Kunii

An Adaptive Hierarchical Routing Protocol

Authors: Wei-Tek Tsai, C. V. Ramamoorthy, Wei Kang Tsai, Osamu Nishiguchi

The Stack Growth Function: Cache Line Reference Models

Authors: Makoto Kobayashi and Myron H. MacDougall

CPC (Cyclic Pipeline Computer) - An Architecture Suited for Josephson and Pipelined-Memory Machines

Authors: Kentaro Shimizu, Eiichi Goto, Shuichi Ichikawa

Tolerance of Double-Loop Computer Networks to Multinode Failures

Authors: Hiroshi Masuyama and Tetsuo Ichimori

Temporal Petri Nets and Their Application to Modeling and Analysis of a Handshake Daisy Chain Arbiter

Authors: Ichiro Suzuki and Harngdar Lu

On the Optimal Design of Multiple-Valued PLA's

Author: Tsutomu Sasao

K-Way Bitonic Sort

Authors: Toshio Nakatani, Shing-Tsaan Huang, Bruce W. Arden, Satish K. Tripathi

Criteria for Selecting a Variable in the Construction of Efficient Decision Trees

Author: Masahiro Miyakawa

1988

High-Speed CAM-Based Architecture for a Prolog Machine (ASCA)

Authors: Jiro Naganuma, Takeshi Ogura, Shin-Ichiro Yamada, Takashi Kimura

Relationship Between P-Valued Majority Functions and P-Valued Threshold Functions

Authors: Yoshinori Yamamoto and Shiro Fujita

Meaningful Special Classes of Ternary Logic Functions - Regular Ternary Logic Functions and Ternary Majority Functions

Authors: Yoshinori Yamamoto and Masao Mukaidono

Equilibrium Point Analysis of Memory Interference in Multiprocessor Systems

Author: Akira Fukuda

A Single Chip Parallel Multiplier by MOS Technology

Authors: Shinji Nakamura and Kai-Yu Chu

Error/Secure/Propagating Concept and its Application to the Design of Strongly Fault-Secure Processors

Authors: Takashi Nanya and Toshiaki Kawamura

1987

On Error Indication for Totally Self-Checking Systems

Authors: Takashi Nanya and Toshiaki Kawamura

On-Line Error-Detectable High-Speed Multiplier Using Redundant Binary Representation and Three-Rail Logic

Authors: Naofumi Takagi and Shuzo Yajima

A Construction Method of High-Speed Decoders Using ROMS's for Bose-Chaudhuri-Hocquenghem and Reed-Solomon Codes

Authors: Hirokazu Okano and Hideki Imai

A Note on Strongly Fault-Secure Sequential Circuits

Authors: Takashi Nanya and Toshiaki Kawamura

Binary Search Revisited: Another Advantage of Fibonacci Search

Authors: Seiichi Nishihara and Hiroji Nishino

New Methods for Realizing Plural Near-Native Performance Virtual Machines

Authors: Hidenori Umeno and Shunji Tanaka

Asignment of Job Modules onto Array Processors

Authors: Kunio Fukunaga, Shoichiro Yamada, Tamotsu Kasai

Design of a Functionally Distributed, Multiprocessor Database Machine Using Data Flow Analysis

Authors: Takanobu Baba, S. Bing Yao, Alan R. Hevner

A New Built-In Self-Test Design for PLA's with High Fault Coverage and Low Overhead

Authors: Robert P. Treuer, Vinod K. Agarwal, Hideo Fujiwara

Inverter-Minimum Networks

Author: Keijiro Nakamura

A Self-Checking Generalized Prediction Checker and Its Use for Built-In Testing

Authors: Eiji Fujiwara and Kohji Matsuoka

1986

An Algorithm for Determining the Fault Diagnosability of a System

Authors: Jagannathan Narasimhan and Kazuo Nakajima

Built-In Testing of Memory Using an On-Chip Compact Testing Scheme

Authors: Kozo Kinoshita and Kewal K. Saluja

An Empirical Study of Task Switching Locality in MVS

Author: Makoto Kobayashi

Algorithms for Iterative Array Multiplication

Author: Shinji Nakamura

Properties of Wired Logic

Authors: Yahiko Kambayashi and Saburo Muroga

Complexity Based on Partitioning of Boolean Circuits and Their Relation to Multivalued Circuits

Author: Akira Maruoka

Regular Ternary Logic Functions - Ternary Logic Functions Suitable for Treating Ambiguity

Author: Masao Mukaidono

The Current Mode Fuzzy Logic Integrated Circuits Fabricated by the Standard CMOS Process

Authors: Takeshi Yamakawa and Tsutomu Miki

1985

Nonbinary Arithmetic AN Codes Using Odd Radix Expressions

Authors: Ryosaku Shimada, Yoshiteru Ohkura, Jun-ichi Aoe

High-Speed VLSI Multiplication Algorithm with a Redundant Binary Addition Tree

Authors: Naofumi Takagi, Hiroto Yasuura, Shuzo Yajima

Generation of a Precise Binary Logarithm with Difference Grouping Programmable Logic Array

Authors: Hao-Yung Lo and Yoshinao Aoki

Connectivity of Regular Directed Graphs with Small Diameters

Authors: Makoto Imase, Terunao Soneoka, Keiji Okada

Test Pattern Generation for API Faults in RAM

Authors: Kewal K. Saluja and Kozo Kinoshita

An Algorithm to Derive the Complement of a Binary Function with Multiple-Valued Inputs

Author: Tsutomu Sasao

Test Procedure Optimization for Layered Protocol Implementations

Authors: Tsukasa Kawaoka and Yoshikane Takahashi

1984

Practical Multiprocessor Scheduling Algorithms for Efficient Parallel Processing

Authors: Hironori Kasahara and Seinosuke Narita

Input Variable Assignment and Output Phase Optimization of PLA's

Author: Tsutomu Sasao

Evaluation of Associative Memory Using Parallel Chained Hashing

Authors: Kei Hiraki, Kenji Nishida, Toshio Shimada

A New PLA Design for Universal Testability

Author: Hideo Fujiwara

A Class of Odd-Weight-Column SEC-DED-SbED Codes for Memory System Applications

Author: Shigeo Kaneda

Stuck-At Fault Tests in the Presence of Undetectable Bridging Faults

Authors: Teruhiko Yamada and Takashi Nanya

A Self-Testing Group-Parity Prediction Checker and Its Use for Built-In Testing

Authors: Eiji Fujiwara, Nobuo Mutoh, Kohji Matsuoka

Area-Time Optimal Fast Implementation of Several Functions in a VLSI Model

Authors: Kouichi Wada, Kenichi Hagihara, Nobuki Tokura

A Representation of Hypergraphs in the Euclidean Space

Authors: Kunio Fukunaga, Shoichiro Yamada, Harold S. Stone, Tamotsu Kasai

On Adaptive System Diagnosis

Authors: S. Louis Hakimi and Kazuo Nakajima

Dynamic Characteristics of Loops

Author: Makoto Kobayashi

1983

On the Acceleration of Test Generation Algorithms

Authors: Hideo Fujiwara and Takeshi Shimono

An Easily Testable Design of Programmable Logic Arrays for Multiple Faults

Authors: Kewal K. Saluja, Kozo Kinoshita, Hideo Fujiwara

Global Compaction of Horizontal Microprogams Based on the Generalized Data Dependency Graph

Authors: Sadahiro Isoda, Yoshizumi Kobayashi, Toru Ishida

Parallel Binary Adders with a Minimum Number of Connections

Authors: Akito Sakurai and Saburo Muroga

Dynamic Profile of Instruction Sequences for the IBM System/370

Author: Makoto Kobayashi

A Two's Complement Array Multiplier Using True Values of the Operands

Authors: Nuno Bandeira, Ken Vaccaro, James A. Howard

A Design for Directed Graphs with Minimum Diameter

Authors: Makoto Imase and Masaki Itoh

Stability and Performance of the R-ALOHA Packet Broadcast System

Author: Shuji Tasaka

Comments on "Detection Location of Input and Feedback Bridging Faults Among Input Output Lines"

Authors: Teruhiko Yamada and Takashi Nanya

Error Analysis of Certain Floating-Point On-Line Algorithms

Authors: Osaaki Watanuki and Milos D. Ercegovac

1982

A Two-Level Microprogrammed Multiprocessor Computer with Nonnumeric Functions

Authors: Takanobu Baba, Ken Ishikawa, Kenzo Okuda

Lower Bounds on Crosspoints in Concentrators

Authors: Shinji Nakamura and Gerald M. Masson

The Parallel Enumeration Sorting Scheme for VLSI

Authors: Hiroto Yasuura, Naofumi Takagi, Shuzo Yajima

PICCOLO Logic for a Picture Database Computer and Its Implementation

Authors: Kazunori Yamaguchi and Tosiyasu L. Kunii

A Data Flow Computer Architecture with Program and Token Memories

Authors: Masahiro Sowa and Tadao Murata

Single Byte Error Correcting - Double Byte Error Detecting Codes for Memory Systems

Authors: Shigeo Kaneda and Eiji Fujiwara

The Complexity of Fault Detection Problems for Combinational Logic Circuits

Authors: Hideo Fujiwara and Shunichi Toida

Single Asymmetric Error-Correcting Cyclic AN Codes

Author: Akira Shiozaki

Correction to "Error-Correcting Parsers for Formal Languages"

Authors: Eiichi Tanaka and King-sun Fu

Deadlock-Free Systems for a Bounded Number of Processes

Authors: Toshihide Ibaraki and Tsunehiko Kameda

A Task Allocation Model for Distributed Computing Systems

Authors: Perng-Yi Richard Ma, Edward Y. S. Lee, Masahiro Tsuchiya

1981

A Design of Programmable Logic Arrays with Universal Tests

Authors: Hideo Fujiwara and Kozo Kinoshita

An Improvement of Reliability of Memory System with Skewing Reconfiguration

Author: Takeo Kanai

Multiple-Valued Decomposition of Generalized Boolean Functions and the Complexity of Programmable Logic Arrays

Author: Tsutomu Sasao

On Closedness and Test Complexity of Logic Circuits

Author: Hideo Fujiwara

A Layout System for the Random Logic Portion of an MOS LSI Chip

Authors: Isao Shirakawa, Noboru Okuda, Takashi Harada, Sadahiro Tani, Hiroshi Ozaki

Optimization of Microprograms

Authors: Mario Tokoro, Euji Tamura, Takashi Takizuka

The MPG System: A Machine-Independent Efficient Microprogram Generator

Authors: Takanobu Baba and Hiroshi Hagiwara

Design to Minimize Diameter on Building-Block Network

Authors: Makoto Imase and Masaki Itoh

Optimal Layout of CMOS Functional Arrays

Authors: Takao Uehara and William M. van Cleemput

On Minimal Test Sets for Locating Single Link Failures in Networks

Authors: Toshihide Ibaraki, Tsunehiko Kameda, Shunichi Toida

Rewritable Progammable Logic Array of Current Mode Logic

Authors: Mamoru Tanaka, Shinji Ozawa, Shinsaku Mori

1980

An Approach to Gate Assignment and Module Placement for Printed Wiring Boards

Authors: Ikuo Nishioka, Takuji Kurimoto, Seiji Yamamoto, Toru Chiba, Isao Shirakawa, Hiroshi Ozaki

A Method for Minimizing Incompletely Specified Sequential Machines

Author: Masaru Yamamoto

A Dynamically Microprogammable Computer with Low-Level Parallelism

Authors: Hiroshi Hagiwara, Shinji Tomita, Shigeru Oyanagi, Kiyoshi Shibayama

Sequential Machines Having Quasi-Stable States

Author: Takeomi Tamesada

A Symmetric Cosine Transform

Author: Hideo Kitajima

An NMOS Microcomputer Peripheral Interface Unit Incorporating an Analog-to-Digital Converter

Authors: Tsuneo Funabashi, Katsuaki Takagi, Toshiro Tsukada, Hideo Nakamura, Michio Hara

The Development of a Bubble Memory Controller for Low-Cost File Use

Authors: Yuzo Kita, Noboru Yamaguchi, Mamoru Sugie, Shigeru Yoshizawa

1979

Universal Multicode STT State Assignments for Asynchronous Sequential Machines

Authors: Takashi Nanya and Yoshihiro Tohma

Synthesis of Gate-Minimum Multi-Output Two-Level Negative Gate Networks

Author: Keijiro Nakamura

A High-Speed Algorithm for the Generation of Straight Lines and Circular Arcs

Authors: Yasuhito Suenaga, Takahiko Kamae, Tomonori Kobayashi

Logic Design of Programmable Logic Arrays

Author: Yahiko Kambayashi

Conservative Logic Elements and Their Universality

Authors: Tsutomu Sasao and Kozo Kinoshita

On the Number of Multivalued Switching Functions Realizable by Cascades

Authors: Teruo Hikita and Hajime Enomoto

Results of the Synthesis of Optimal Networks of AND and OR Gates for Four-Variable Switching Functions

Authors: Jay Niel Culliney, Ming Huei Young, Tomoyasu Nakagawa, Saburo Muroga

On the Number of Fanout-Free Functions and Unate Cascade Functions

Authors: Tsutomu Sasao and Kozo Kinoshita

1978

On the Computational Complexity of System Diagnosis

Authors: Hideo Fujiwara and Kozo Kinoshita

Texture Characterization and Texture-Based Image Partitioning Using Two-Dimensional Linear Estimation Technique

Authors: Koichiro Deguchi and Iwao Morishita

A Synthesizing Method for Large Parallel Counters with a Network of Smaller Ones

Authors: Hideaki Kobayashi and Hiroyoshi Ohara

On Universal Single Transition Time Asynchronous State Assignments

Authors: Takashi Nanya and Yoshihiro Tohma

Realization of Minimum Circuits with Two-Input Conservative Logic Elements

Authors: Tsutomu Sasao and Kozo Kinoshita

Detection of Ellipses by a Modified Hough Transformation

Authors: Saburo Tsuji and Fumio Matsumoto

Error-Correcting Parsers for Formal Languages

Authors: Eiichi Tanaka and King-sun Fu

Classification of the Keyhole Shaped Tombs by Template Matching Method

Author: Kazumasa Ozawa

Impact of the LSI on High-Speed Computer Packaging

Author: Tsuneyo Chiba

Some Existence Theorems for Probabilistically Diagnosable Systems

Authors: Hideo Fujiwara and Kozo Kinoshita

Connection Assignments for Probabilistically Diagnosable Systems

Authors: Hideo Fujiwara and Kozo Kinoshita

Cascade Realization of 3-Input 3-Output Conservative Logic Circuits

Authors: Tsutomu Sasao and Kozo Kinoshita

On Some Dynamical Properties of Finite Cellular Automaton

Authors: Masateru Harao and Shoichi Noguchi

Comments on "A Measure of Computational Work" and "Logical Network Cost and Entropy"

Author: Kenichi Mase

1977

Static-Hazard-Free T-Gate for Ternary Memory Element and Its Application to Ternary Counters

Authors: Tatsuo Higuchi and Michitaka Kameyama

On Multivalued Multithreshold Networks Composed of Conventional Threshold Elements

Author: Okihiko Ishizuka

Synthesis of Multithreshold Tree Networks

Author: Okuhiko Ishizuka

Synthesis of Multiple-Valued Logic Networks Based on Tree-Type Universal Logic Module

Authors: Michitaka Kameyama and Tatsuo Higuchi

An Optimal Orthogonal Expansion for Classification of Patterns

Authors: Yatsuka Nakamura, Masakazu Furuya, Shoichi Sunohara

A Versatile Machine Vision System for Complex Industrial Parts

Authors: Masahiko Yachida and Saburo Tsuji

A Wire-Routing Scheme Based on Trunk-Division Methods

Authors: Tetsuo Asano, Tadahiro Kitahashi, Kokichi Tanaka, Hiroshi Horino, Nobutaka Amano

1976

Nonparametric Learning Without a Teacher Based on Mode Estimation

Authors: Riichiro Mizoguchi and Masamichi Shimura

A Relationship Between Two Types of Two-Layer Threshold-Element Pattern-Recognition Networks

Author: Ryuzo Takiyama

System Diagnosis and Redundant Tests

Author: Shunichi Toida

Toward Optimization of Horizontal Microprograms

Authors: Masahiro Tsuchiya and Mario J. Gonzalez

A Note on the Linear Space Automata Stability Problem

Authors: Kazue Sugino, Yasuyoshi Inagaki, Teruo Fukumura

On Magnetic Bubble Logic Circuits

Authors: Kozo Kinoshita, Tsutomu Sasao, Jun Matsuda

A Method for the Correction of Garbled Words Based on the Levenshtein Metric

Authors: Teruo Okuda, Eiichi Tanaka, Tamotsu Kasai

1975

Comments on "Checking Experiments for Sequential Machines"

Authors: Y. Wakimura and Nobuaki Yoshida

An Approach to the Diagnosability Analysis of a System

Authors: F. J. Allan, Tiko Kameda, Shunichi Toida

An Approach to Unsupervised Learning Classification

Authors: Riichiro Mizoguchi and Masamichi Shimura

A New Voltage to Frequency Converter

Authors: Keiji Taniguchi and Takanori Sakai

Easily Testable Sequential Machines with Extra Inputs

Authors: Hideo Fujiwara, Yoich Nagao, Tsutomu Sasao, Kozo Kinoshita

The Range of Logical Flexibility of Tree Networks

Authors: Akira Maruoka and Namio Honda

1974

Design Technique of Fail-Safe Sequential Circuits Using Flip-Flops For Internal Memory

Author: Yoshihiro Tohma

Comments on "Monotone Functions in Sequential Circuits"

Author: Toshihide Ibaraki

A High-Level Language for Horizontal Microprogramming

Authors: C. V. Ramamoorthy and Masahiro Tsuchiya

A Method for the Realization of Fail-Safe Asynchronous Sequential Circuits

Authors: Y. Mukai and Yoshihiro Tohma

Design of Diagnosable Sequential Machines Utilizing Extra Outputs

Authors: Hideo Fujiwara and Kozo Kinoshita

Power Minimization Problems of Logic Networks

Authors: Shuzo Yajima and Kosaku Inagaki

Floating-Point Arithmetic Algorithms in the Symmetric Residue Number System

Authors: Eisuke Kinoshita, Hideo Kosako, Yoshiaki Kojima

1973

Macro E-Nets for Representation of Parallel Systems

Authors: Jerre D. Noe and Gary J. Nutt

The Parallel Evaluation of Arithmetic Expressions Without Division

Authors: Richard Brent, Daniel Kuck, Kiyoshi Maruyama

Logical Networks of Flexible Cells

Authors: Akira Maruoka and Namio Honda

General Division in the Symmetric Residue Number System

Authors: Eisuke Kinoshita, Hideo Kosako, Yoshiaki Kojima

On the Parallel Evaluation of Polynomials

Author: Kiyoshi M. Maruyama

1972

On the Number of Operations Simultaneously Executable in Fortran-Like Programs and Their Resulting Speedup

Authors: David J. Kuck, Yoichi Muraoka, Shyh-Ching Chen

Learning Patterns and Pattern Sequences by Self-Organizing Nets of Threshold Elements

Author: Shun-ichi Amari

N-Fail-Safe Sequential Machines

Authors: Tadao Takaoka and Toshihide Ibaraki

Design of Optimal Switching Networks by Integer Programming

Authors: Saburo Muroga and Toshihide Ibaraki

Sequential Permutation Networks

Author: Kazuaki Harada

Enumeration of Ternary Threshold Functions of Three Variables

Authors: Tsunehiro Aibara and Michihiro Akagi

A Prototype Intelligent Robot that Assembles Objects from Plan Drawings

Authors: Masakazu Ejiri, Takeshi Uno, Haruo Yoda, Tatsuo Goto, Kiyoo Takeyasu

Orthogonal Expansion of Many-Valued Logical Functions and its Application to their Realization with a Single-Threshold Element

Authors: Tadahiro Kitahashi and Kohkichi Tanaka